Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752831AbcDOQnT (ORCPT ); Fri, 15 Apr 2016 12:43:19 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14858 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751574AbcDOQnR (ORCPT ); Fri, 15 Apr 2016 12:43:17 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 15 Apr 2016 09:40:29 -0700 Message-ID: <57111778.5030500@nvidia.com> Date: Fri, 15 Apr 2016 22:01:52 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Stephen Warren CC: , , , , , , , , , Subject: Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control References: <1460473007-11535-1-git-send-email-ldewangan@nvidia.com> <1460473007-11535-7-git-send-email-ldewangan@nvidia.com> <5711183F.1090003@wwwdotorg.org> In-Reply-To: <5711183F.1090003@wwwdotorg.org> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRHKMAIL103.nvidia.com (10.25.59.17) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 990 Lines: 22 On Friday 15 April 2016 10:05 PM, Stephen Warren wrote: > On 04/12/2016 08:56 AM, Laxman Dewangan wrote: >> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V >> or 3.3V I/O voltage levels. Also IO pads can be configured for >> power down state if it is not in used. SW needs to configure the >> voltage level of IO pads based on IO rail voltage and its power >> state based on platform usage. >> >> Add DT binding document for detailing the DT properties for >> configuring IO pads voltage levels and its power state. > > I hope that we only intend to use this in the case where Linux must > make dynamic changes to the IO voltage (e.g. SD cards switching > between speeds). > > All static settings, and good boot defaults, should be set up by > system FW. Perhaps not all FW does this on Tegra210 platforms:-( I > hope that on future chips, the same FW that sets up the static pinmux > sets up the static IO voltage configuration, in exactly the same way. Exactly yes.