Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751177AbcDPHiM (ORCPT ); Sat, 16 Apr 2016 03:38:12 -0400 Received: from down.free-electrons.com ([37.187.137.238]:47278 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751079AbcDPHiK convert rfc822-to-8bit (ORCPT ); Sat, 16 Apr 2016 03:38:10 -0400 Date: Sat, 16 Apr 2016 09:38:06 +0200 From: Boris Brezillon To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= Cc: linux-mtd@lists.infradead.org, Haavard Skinnemoen , Hans-Christian Egtvedt , Alexandre Belloni , Nicolas Ferre , Greg Kroah-Hartman , Marc Kleine-Budde , Alan Stern , linux-kernel@vger.kernel.org (open list) Subject: Re: [PATCH 03/12] avr32: set Atmel NAND ECC algorithm explicitly Message-ID: <20160416093806.7da3d660@bbrezillon> In-Reply-To: <1460750052-16285-4-git-send-email-zajec5@gmail.com> References: <1460750052-16285-1-git-send-email-zajec5@gmail.com> <1460750052-16285-4-git-send-email-zajec5@gmail.com> X-Mailer: Claws Mail 3.12.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2375 Lines: 62 On Fri, 15 Apr 2016 21:54:03 +0200 Rafał Miłecki wrote: > This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to > enum nand_ecc_algo). Not sure we really need to add this ->ecc_algo field: none of the existing AVR32 boards use software BCH implementation, and I don't expect to see new AVR32 boards :-). How about setting NAND_ECC_HAMMING when ecc_mode == NAND_ECC_SOFT directly in the atmel_nand driver? > > Signed-off-by: Rafał Miłecki > --- > arch/avr32/boards/atngw100/setup.c | 1 + > arch/avr32/boards/atstk1000/atstk1002.c | 1 + > include/linux/platform_data/atmel.h | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c > index afeae89..b059b97 100644 > --- a/arch/avr32/boards/atngw100/setup.c > +++ b/arch/avr32/boards/atngw100/setup.c > @@ -98,6 +98,7 @@ static struct atmel_nand_data atngw100mkii_nand_data __initdata = { > .enable_pin = GPIO_PIN_PE(23), > .bus_width_16 = true, > .ecc_mode = NAND_ECC_SOFT, > + .ecc_algo = NAND_ECC_HAMMING, > .parts = nand_partitions, > .num_parts = ARRAY_SIZE(nand_partitions), > }; > diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c > index 6c80aba..6b45faf 100644 > --- a/arch/avr32/boards/atstk1000/atstk1002.c > +++ b/arch/avr32/boards/atstk1000/atstk1002.c > @@ -96,6 +96,7 @@ static struct atmel_nand_data atstk1006_nand_data __initdata = { > .rdy_pin = GPIO_PIN_PB(30), > .enable_pin = GPIO_PIN_PB(29), > .ecc_mode = NAND_ECC_SOFT, > + .ecc_algo = NAND_ECC_HAMMING, > .parts = nand_partitions, > .num_parts = ARRAY_SIZE(nand_partitions), > }; > diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h > index 3c8825b..a283b3d 100644 > --- a/include/linux/platform_data/atmel.h > +++ b/include/linux/platform_data/atmel.h > @@ -33,6 +33,7 @@ struct atmel_nand_data { > u8 cle; /* address line number connected to CLE */ > u8 bus_width_16; /* buswidth is 16 bit */ > u8 ecc_mode; /* ecc mode */ > + enum nand_ecc_algo ecc_algo; /* ecc algorithm */ > u8 on_flash_bbt; /* bbt on flash */ > struct mtd_partition *parts; > unsigned int num_parts; -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com