Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754795AbcDRC7f (ORCPT ); Sun, 17 Apr 2016 22:59:35 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:45275 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754630AbcDRC7d (ORCPT ); Sun, 17 Apr 2016 22:59:33 -0400 Subject: Re: [RESEND PATCH v10 2/6] clk: hisilicon: add CRG driver for hi3519 soc To: Stephen Boyd References: <1459411811-12390-1-git-send-email-xuejiancheng@hisilicon.com> <1459411811-12390-3-git-send-email-xuejiancheng@hisilicon.com> <57104449.8090506@huawei.com> <20160416004130.GO26353@codeaurora.org> CC: , , , , , , , , , , , , , , , Zhangfei Gao From: Jiancheng Xue Message-ID: <57144D87.30401@huawei.com> Date: Mon, 18 Apr 2016 10:59:19 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: <20160416004130.GO26353@codeaurora.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.217.211] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.57144D82.0081,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b5dff9bf377328a8fe391dc024097b25 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1135 Lines: 32 Hi Stephen, On 2016/4/16 8:41, Stephen Boyd wrote: > On 04/15, Jiancheng Xue wrote: >> Hi, >> >> On 2016/3/31 16:10, Jiancheng Xue wrote: >>> From: Jiancheng Xue >>> >>> The CRG(Clock and Reset Generator) block provides clock >>> and reset signals for other modules in hi3519 soc. >>> >>> Signed-off-by: Jiancheng Xue >>> Acked-by: Rob Herring >>> Acked-by: Philipp Zabel >>> --- >> I hope this patchset can be merged through arch/arm tree >> The dts binding part has been acked by Rob Herring, and >> the reset part has been acked by Philipp Zabel. Could you >> help me to ack this whole clk patch? Please also let me >> know if this patch still have issues. Thank you very much! > > Can I merge it through clk tree and make a stable branch to pull > through arm-soc? I assume another patch is coming but it's good > to get clarity before then. > Yes. It's also OK for me if this patchset can be merged into mainline Finally. Then can I send reset controller driver, clock driver and arm-soc patches separately? Regards, Jiancheng