Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752084AbcDRJga (ORCPT ); Mon, 18 Apr 2016 05:36:30 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:43122 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751905AbcDRJg3 (ORCPT ); Mon, 18 Apr 2016 05:36:29 -0400 From: Paul Burton To: , Ralf Baechle CC: James Hogan , "Steven J . Hill" , Paul Burton , "Paul Gortmaker" , Subject: [PATCH v2 02/13] MIPS: Fix HTW config on XPA kernel without LPA enabled Date: Mon, 18 Apr 2016 10:35:22 +0100 Message-ID: <1460972133-16973-3-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1460972133-16973-1-git-send-email-paul.burton@imgtec.com> References: <1460972133-16973-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.100.200.164] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1483 Lines: 42 From: James Hogan The hardware page table walker (HTW) configuration is broken on XPA kernels where XPA couldn't be enabled (either nohtw or the hardware doesn't support it). This is because the PWSize.PTEW field (PTE width) was only set to 8 bytes (an extra shift of 1) in config_htw_params() if PageGrain.ELPA (enable large physical addressing) is set. On an XPA kernel though the size of PTEs is fixed at 8 bytes regardless of whether XPA could actually be enabled. Fix the initialisation of this field based on sizeof(pte_t) instead. Fixes: c5b367835cfc ("MIPS: Add support for XPA.") Signed-off-by: James Hogan Cc: Ralf Baechle Cc: Steven J. Hill Cc: linux-mips@linux-mips.org Signed-off-by: Paul Burton --- Changes in v2: None arch/mips/mm/tlbex.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 84c6e3f..86aa7c2 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -2311,9 +2311,7 @@ static void config_htw_params(void) if (CONFIG_PGTABLE_LEVELS >= 3) pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; - /* If XPA has been enabled, PTEs are 64-bit in size. */ - if (config_enabled(CONFIG_64BITS) || (read_c0_pagegrain() & PG_ELPA)) - pwsize |= 1; + pwsize |= ilog2(sizeof(pte_t)/4) << MIPS_PWSIZE_PTEW_SHIFT; write_c0_pwsize(pwsize); -- 2.8.0