Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752103AbcDRKL2 (ORCPT ); Mon, 18 Apr 2016 06:11:28 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:50878 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbcDRKLY (ORCPT ); Mon, 18 Apr 2016 06:11:24 -0400 Date: Mon, 18 Apr 2016 11:11:17 +0100 From: Mark Brown To: Scott Wood Cc: Po Liu , "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" Message-ID: <20160418101117.GP3217@sirena.org.uk> References: <1460545402-8162-1-git-send-email-po.liu@nxp.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="movZSYdJ761vCHaE" Content-Disposition: inline In-Reply-To: X-Cookie: Tomorrow, you can be anywhere. User-Agent: Mutt/1.5.24 (2015-08-30) X-SA-Exim-Connect-IP: 2a01:348:6:8808:fab::3 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH] dspi: config dspi master regmap with right mode depend on BE or LE X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1495 Lines: 37 --movZSYdJ761vCHaE Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Apr 17, 2016 at 02:41:40AM +0000, Scott Wood wrote: > Looking more closely, the binding has a big-endian property. It says > the default if that property is absent is native endian, which is > insane. Fix the binding to say that little endian is the default (this > change shouldn't break any existing trees), and make sure that's what > the code implements. I think you need val_format_endian_default, not > val_format_endian. The binding defaults to little endian and (in implmentation terms) always has done though that used to be unintentional. There *are* a reasonable number of devices out there which are native endian, for example most of the MIPS chips switch the endianness of the entire chip rather than just the CPU, but most of the current usage has been on ARM devices which only switch the core. --movZSYdJ761vCHaE Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJXFLLEAAoJECTWi3JdVIfQmCsH/Rky0sbE5P5ZmAaq30LBa4/8 DgTx093CeYON+ZOomSajn8X9PB3F/rOWuHIm8JCNI8VuWOP1GBA1IN4eknuCRCwd y6tA+1c5Fl8I3vYLpUUAEGfSo+CCsvFeMHzzlWCaCmOWpKxIkoBaPFeV70+V5mtH U2i78vEQ2GRkTAcKtsfGC12fR/54IOfFkOO87rSzVZmyTXIDMkd8Y37n+aFcWgyi 8GOY/DfyTyDUuRkWbqJLx7SjXLKh/Xw85m7CnhEKefnwdSMaZVXWVVRGCcccdX8R YjLELrTstLYQQcV0kbH0lLsBqqUBZKdRllCtZgf8d/uieVhhzm/EHSMkXY8vOF8= =OHy8 -----END PGP SIGNATURE----- --movZSYdJ761vCHaE--