Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751831AbcDRTgY (ORCPT ); Mon, 18 Apr 2016 15:36:24 -0400 Received: from saturn.retrosnub.co.uk ([178.18.118.26]:60726 "EHLO saturn.retrosnub.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751405AbcDRTgX (ORCPT ); Mon, 18 Apr 2016 15:36:23 -0400 Subject: Re: [PATCH 1/5] max44000: Initial commit To: Mark Brown , Crestez Dan Leonard References: <5dbbd82290c575f595ae0907aaf8e03117a6d017.1460045763.git.leonard.crestez@intel.com> <570A513A.4020106@kernel.org> <570BBDFC.6010601@intel.com> <57134AFA.3040406@kernel.org> <20160418103212.GQ3217@sirena.org.uk> <5714CFFA.2080309@intel.com> <20160418123451.GB3217@sirena.org.uk> Cc: Peter Meerwald-Stadler , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Hartmut Knaack , Lars-Peter Clausen , Daniel Baluta From: Jonathan Cameron Message-ID: <57153733.1070605@kernel.org> Date: Mon, 18 Apr 2016 20:36:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.1 MIME-Version: 1.0 In-Reply-To: <20160418123451.GB3217@sirena.org.uk> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1155 Lines: 27 On 18/04/16 13:34, Mark Brown wrote: > On Mon, Apr 18, 2016 at 03:15:54PM +0300, Crestez Dan Leonard wrote: > >> As a further clarification: regmap_write will write to hardware even if >> the cache is known to be up-to-date and no matter the regcache_type. Did >> I understand this correctly? > >> I'm basing this on reading the code, it seems to me that map->reg_write >> is only avoided on error paths or if map->cache_only is set to true. > >> This always-write guarantee is not obvious and if it's OK for drivers to >> rely on it perhaps it should be explicitly documented on regmap_write. > > Yes. I have to say that you are the first person I've encountered who > has been confused by this, I'm not sure why you'd expect writes to be > discarded. > It confused me too :) To my mind a classic cache optimization would be to not write to the hardware if the value is already known to be as desired. Still, I guess it would add another check to identify which registers you really wanted to hammer whatever vs which can be assumed not to read the write is not worth the effort for this case that inherently won't be hit that often. Jonathan