Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753210AbcDSId7 (ORCPT ); Tue, 19 Apr 2016 04:33:59 -0400 Received: from spamalot.elettra.trieste.it ([140.105.206.208]:52903 "EHLO spamalot.elettra.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751904AbcDSId5 (ORCPT ); Tue, 19 Apr 2016 04:33:57 -0400 MIME-Version: 1.0 In-Reply-To: <1461039981.32510.201.camel@buserror.net> References: <460384482-21320-1-git-send-email-alessio.bogani@elettra.eu> <1460966279-29188-1-git-send-email-alessio.bogani@elettra.eu> <1461039981.32510.201.camel@buserror.net> Date: Tue, 19 Apr 2016 10:33:47 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/1] powerpc/86xx: Add support for Emerson/Artesyn MVME7100 From: Alessio Igor Bogani To: Scott Wood Cc: Kumar Gala , linuxppc-dev@lists.ozlabs.org, LKML Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2007 Lines: 64 Hi Scott, Thanks for reviewing it! On 19 April 2016 at 06:26, Scott Wood wrote: > On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote: >> + pci0: pcie@f1008000 { >> + reg = <0xf1008000 0x1000>; >> + ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 >> 0x50000000 >> + 0x01000000 0x0 0x00000000 0xf0000000 0x0 >> 0x00800000>; [...] >> + >> + pci1: pcie@f1009000 { >> + compatible = "fsl,mpc8641-pcie"; >> + device_type = "pci"; >> + #size-cells = <2>; >> + #address-cells = <3>; >> + reg = <0xf1009000 0x1000>; >> + bus-range = <0 0xff>; > > Why are pci0 and pci1 so different? Why does mpc8641si-post.dtsi not have pci1? You are right. The MPC8641 processor offers two pci so mpc8641si-post.dtsi should be the right place where to define both. What about the boards which don't use the pci1? Will 'status = "disabled"' be enough? >> +asm(" .globl _zimage_start\n\ >> + _zimage_start:\n\ >> + mfmsr 10\n\ >> + rlwinm 10,10,0,~(1<<15) /* Clear MSR_EE */\n\ >> + sync\n\ >> + mtmsr 10\n\ >> + isync\n\ >> + b _zimage_start_lib\n\ >> +"); > > Please put this in an asm file. Ok. > Is U-Boot really not clearing MSR[EE]? How old is this U-Boot? [...] >> + defined(TARGET_83xx) || defined(TARGET_MVME7100) >> unsigned long bi_immr_base; /* base of IMMR register [...] > TARGET_86xx would match the U-Boot definition better. [...] >> + _set_L2CR(_get_L2CR() | L2CR_L2E); [...] > U-Boot doesn't enable L2 cache? In fact it isn't U-Boot but MotLoad which it doesn't clear MSR[EE] and disable L2 cache just before pass control to operating system. It seems to be partially compatible with older version of U-Boot (boot/mvme7100.c) but I wasn't able to use an uImage to boot so I have switched to the dtbImage target. Thanks! Ciao, Alessio