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Date: Tue, 19 Apr 2016 11:16:05 +0200
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>, David Airlie <airlied@linux.ie>,
        Thierry Reding <thierry.reding@gmail.com>,
        Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
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        Boris Brezillon <boris.brezillon@free-electrons.com>,
        Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
        Rob Clark <robdclark@gmail.com>
Subject: Re: [PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates
 compatible
Message-ID: <20160419091605.GW4005@lukather>
References: <1458751122-23976-1-git-send-email-maxime.ripard@free-electrons.com>
 <1458751122-23976-6-git-send-email-maxime.ripard@free-electrons.com>
 <20160415222911.GR14441@codeaurora.org>
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On Fri, Apr 15, 2016 at 03:29:11PM -0700, Stephen Boyd wrote:
> On 03/23, Maxime Ripard wrote:
> > The Allwinner SoCs have a gate controller to gate the access to the DRAM
> > clock to the some devices that need to access the DRAM directly (mostly
> > display / image related IPs).
> >=20
> > Use a simple gates driver to support the one found in the A13 / R8 SoCs.
> >=20
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
>=20
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Applied, thanks!
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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