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Date: Tue, 19 Apr 2016 11:18:23 +0200
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>, David Airlie <airlied@linux.ie>,
        Thierry Reding <thierry.reding@gmail.com>,
        Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
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        dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com,
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        Hans de Goede <hdegoede@redhat.com>,
        Alexander Kaplan <alex@nextthing.co>,
        Boris Brezillon <boris.brezillon@free-electrons.com>,
        Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
        Rob Clark <robdclark@gmail.com>
Subject: Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock
Message-ID: <20160419091823.GX4005@lukather>
References: <1458751122-23976-1-git-send-email-maxime.ripard@free-electrons.com>
 <1458751122-23976-4-git-send-email-maxime.ripard@free-electrons.com>
 <20160415223441.GT14441@codeaurora.org>
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On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote:
> On 03/23, Maxime Ripard wrote:
> > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> > PLL7, clocked from a 3MHz oscillator, that drives the display related
> > clocks (GPU, display engine, TCON, etc.)
> >=20
> > Add a driver for it.
> >=20
> > Acked-by: Rob Herring <robh@kernel.org>
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
>=20
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Applied, thanks!
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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