Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753879AbcDSKBj (ORCPT ); Tue, 19 Apr 2016 06:01:39 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8748 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753263AbcDSKBh (ORCPT ); Tue, 19 Apr 2016 06:01:37 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 19 Apr 2016 02:59:37 -0700 Message-ID: <5715FF36.9040201@nvidia.com> Date: Tue, 19 Apr 2016 15:19:42 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Linus Walleij CC: Stephen Warren , Thierry Reding , Alexandre Courbot , Rob Herring , Mark Rutland , Jon Hunter , "linux-tegra@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" Subject: Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads References: <1460473007-11535-1-git-send-email-ldewangan@nvidia.com> <1460473007-11535-8-git-send-email-ldewangan@nvidia.com> <5710A8A4.90309@nvidia.com> <5710BA75.2010503@nvidia.com> <5710D4E2.2030801@nvidia.com> <5710F3DC.7090906@nvidia.com> In-Reply-To: <5710F3DC.7090906@nvidia.com> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRHKMAIL103.nvidia.com (10.25.59.17) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2115 Lines: 50 Hi Linus, On Friday 15 April 2016 07:29 PM, Laxman Dewangan wrote: > > On Friday 15 April 2016 07:33 PM, Linus Walleij wrote: >> On Fri, Apr 15, 2016 at 1:47 PM, Laxman Dewangan >> wrote: >>> On Friday 15 April 2016 04:45 PM, Linus Walleij wrote: >>>> On Fri, Apr 15, 2016 at 11:55 AM, Laxman Dewangan >>>> >>>> wrote: >>>> But to be sure we would like to know what is actually happening, >>>> electronically speaking, when you set this up. Do you have any >>>> idea? >>> From electronic point of view, the value of VIL, VIH, VOL, VOH >>> (Input/output >>> voltage level for low and high state) are different when talking for >>> 0 t >>> 1.8V and 0 to 3.3V. >> Yeah that I get. But since it is switched on a per-pin basis, and >> this is not about what voltage is actually supplied to the I/O cell, >> because that comes from the outside, it is a mystery why it is >> even needed. >> >> I understand that there is a bit selecting driving voltage level in >> the register range, what I don't understand is what that is >> doing in the I/O cell. >> >> The bit in the register must be routed to somehing in the I/O cell >> and I would like to know what. I take it that an ordinary CMOS >> totem-pole push-pull output is going to work the same with 1.8 >> and 3.3V alike so it's obviously not enabling any extra transistors >> or anything. >> >> > I dont have answer for this now and I need to discuss with HW team to > get this info. > > I will be back here after discussion with HW team. > I had discussion with HW team to get this info from analog point of view. The IO circuitry has to be configured correctly to engage the right level shifting circuits between the IO rail and the core voltage rail in each direction; and that is the main purpose of this configuration. You are correct, the output drivers will naturally drive towards the rails, whatever their voltage may be; and the input receiver will likewise reference itself naturally to the rail, although the switching threshold of the receiver transistors may sometimes need configuration too.