Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752907AbcDSL1K (ORCPT ); Tue, 19 Apr 2016 07:27:10 -0400 Received: from mail-vk0-f53.google.com ([209.85.213.53]:33325 "EHLO mail-vk0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750969AbcDSL1H (ORCPT ); Tue, 19 Apr 2016 07:27:07 -0400 MIME-Version: 1.0 In-Reply-To: <1460804619-2972-1-git-send-email-gabriele.paoloni@huawei.com> References: <1460804619-2972-1-git-send-email-gabriele.paoloni@huawei.com> Date: Tue, 19 Apr 2016 16:57:05 +0530 Message-ID: Subject: Re: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration From: Pratyush Anand To: Gabriele Paoloni Cc: Jingoo Han , linuxarm@huawei.com, "linux-pci@vger.kernel.org" , linux-kernel@vger.kernel.org, Bjorn Helgaas Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 647 Lines: 16 On Sat, Apr 16, 2016 at 4:33 PM, Gabriele Paoloni wrote: > > Currently dw_pcie_setup_rc configures memory base and memory > limit in the type1 configuration header for the root complex. > In doing so it uses the cpu address (pp->mem_base) rather than > the bus address (pp->mem_bus_addr): this is wrong and it is > useless since the configuration is overwritten later on when > pci_bus_assign_resources() is called. > > Therefore this patch just removes this configuration from > dw_pcie_setup_rc. > > Signed-off-by: Gabriele Paoloni Acked-by: Pratyush Anand