Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932188AbcDSOOR (ORCPT ); Tue, 19 Apr 2016 10:14:17 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12508 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754557AbcDSOOO (ORCPT ); Tue, 19 Apr 2016 10:14:14 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 19 Apr 2016 07:12:14 -0700 Subject: Re: [PATCH 05/15] irqchip: Mask the non-type/sense bits when translating an IRQ To: Marc Zyngier References: <1458224359-32665-1-git-send-email-jonathanh@nvidia.com> <1458224359-32665-6-git-send-email-jonathanh@nvidia.com> <20160409120333.3982c53b@arm.com> CC: Thomas Gleixner , Jason Cooper , =?UTF-8?Q?Beno=c3=aet_Cousson?= , Tony Lindgren , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Stephen Warren" , Thierry Reding , Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , , , From: Jon Hunter Message-ID: <57163D2F.5020005@nvidia.com> Date: Tue, 19 Apr 2016 15:14:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <20160409120333.3982c53b@arm.com> X-Originating-IP: [10.21.132.108] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3063 Lines: 77 On 09/04/16 12:03, Marc Zyngier wrote: > On Thu, 17 Mar 2016 14:19:09 +0000 > Jon Hunter wrote: > >> The firmware parameter that contains the IRQ sense bits may also contain >> other data. When return the IRQ type, bits outside of these sense bits >> should be masked. If these bits are not masked and >> irq_create_fwspec_mapping() is called to map an IRQ, then the comparison >> of the type returned from irq_domain_translate() will never match >> that returned by irq_get_trigger_type() (because this function masks the >> none sense bits) and so we will always call irq_set_irq_type() to program >> the type even if it was not really necessary. >> >> Currently, the downside to this is unnecessarily re-programmming the type >> but nevertheless this should be avoided. >> >> The Tegra LIC, TI Crossbar and GIC-V3 irqchips all have client instances >> (from reviewing the device-tree sources) where bits outside the IRQ sense >> bits are set, but do not mask these bits. Therefore, ensure these bits >> are masked for these irqchips. > > For GICv3, this shouldn't be the case. The DT clearly says that the 3rd > field should only contain the trigger description. It looks like people > have been copying their GICv2 DT and simply slapped the v3 description > in the middle, without changing their interrupt specifiers. Duh. Hmmm ... I was just double checking on this for the gic-v3 by wading through the DTS files, and may be there is no issue here. However, looking at the current code it is a bit inconsistent between firmware types ... static int gic_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) { if (is_of_node(fwspec->fwnode)) { if (fwspec->param_count < 3) return -EINVAL; switch (fwspec->param[0]) { case 0: /* SPI */ *hwirq = fwspec->param[1] + 32; break; case 1: /* PPI */ *hwirq = fwspec->param[1] + 16; break; case GIC_IRQ_TYPE_LPI: /* LPI */ *hwirq = fwspec->param[1]; break; default: return -EINVAL; } *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; return 0; } if (is_fwnode_irqchip(fwspec->fwnode)) { if(fwspec->param_count != 2) return -EINVAL; *hwirq = fwspec->param[0]; *type = fwspec->param[1]; return 0; } return -EINVAL; > I guess this patch doesn't hurt though. Yes, it doesn't but I think I will leave this alone for now, given that I can't find a case where this would be a problem. Cheers Jon