Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933593AbcDSQbe (ORCPT ); Tue, 19 Apr 2016 12:31:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5931 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932482AbcDSQbc (ORCPT ); Tue, 19 Apr 2016 12:31:32 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 19 Apr 2016 09:28:30 -0700 Message-ID: <57165AAE.8050108@nvidia.com> Date: Tue, 19 Apr 2016 21:49:58 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Stephen Warren CC: , , , , , Subject: Re: [PATCH V2 3/3] gpio: tegra: Add support for gpio debounce References: <1461059020-25373-1-git-send-email-ldewangan@nvidia.com> <1461059020-25373-3-git-send-email-ldewangan@nvidia.com> <571658CE.1040306@wwwdotorg.org> In-Reply-To: <571658CE.1040306@wwwdotorg.org> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: BGMAIL104.nvidia.com (10.25.59.13) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1010 Lines: 24 On Tuesday 19 April 2016 09:41 PM, Stephen Warren wrote: > On 04/19/2016 03:43 AM, Laxman Dewangan wrote: >> NVIDIA's Tegra210 support the HW debounce in the GPIO >> controller for all its GPIO pins. >> >> Add support for setting debounce timing by implementing the >> set_debounce callback of gpiochip. > >> diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c > >> @@ -327,6 +360,9 @@ static int tegra_gpio_resume(struct device *dev) >> tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); >> tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); >> tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); >> + tegra_gpio_writel(bank->dbc_cnt[p], GPIO_DBC_CNT(gpio)); >> + tegra_gpio_writel(bank->dbc_enb[p], >> + GPIO_MSK_DBC_EN(gpio)); > > Why not just write to the "regular" register rather than the mask > register here... There is no regular register for enabling debounce. Only masked register exist.