Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932330AbcDTHK3 (ORCPT ); Wed, 20 Apr 2016 03:10:29 -0400 Received: from mail-bl2nam02on0078.outbound.protection.outlook.com ([104.47.38.78]:48089 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753680AbcDTHK2 convert rfc822-to-8bit (ORCPT ); Wed, 20 Apr 2016 03:10:28 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Anurag Kumar Vulisha To: Alexandre Belloni CC: Alessandro Zummo , Soren Brinkmann , Michal Simek , "rtc-linux@googlegroups.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Punnaiah Choudary Kalluri , Anirudha Sarangi , Srikanth Vemula , Srinivas Goud Subject: RE: [PATCH 3/3] RTC: Update seconds time programming logic Thread-Topic: [PATCH 3/3] RTC: Update seconds time programming logic Thread-Index: AQHRlLUSCjpso4UInESpOuGO8Xkd/Z+RZtCAgAENi8A= Date: Wed, 20 Apr 2016 07:10:22 +0000 Message-ID: <3802E9A6666DF54886E2B9CBF743BA9825E0B42B@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1460463346-24923-1-git-send-email-anuragku@xilinx.com> <1460463346-24923-3-git-send-email-anuragku@xilinx.com> <20160419223109.GF29844@piout.net> In-Reply-To: <20160419223109.GF29844@piout.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.97.204] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22272.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(13464003)(377454003)(199003)(15975445007)(2900100001)(2906002)(102836003)(3846002)(6806005)(6116002)(23726003)(586003)(46406003)(86362001)(92566002)(2950100001)(4001430100002)(1096002)(5004730100002)(55846006)(11100500001)(5008740100001)(189998001)(107886002)(2920100001)(1220700001)(110136002)(50986999)(5250100002)(76176999)(19580395003)(33656002)(19580405001)(50466002)(4326007)(81166005)(106116001)(87936001)(97756001)(106466001)(63266004)(15650500001)(2420400007)(10710500007)(54356999)(5003600100002)(107986001)(18886065003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT038;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:sfv;MX:1;A:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: d13fc5f0-fefd-46e2-635c-08d368ead8ed X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT038; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521026)(601004)(2401047)(8121501046)(5005006)(13018025)(13024025)(13015025)(13017025)(13023025)(3002001)(10201501046);SRVR:SN1NAM02HT038;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT038; X-Forefront-PRVS: 0918748D70 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2016 07:10:25.7787 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT038 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5304 Lines: 129 Hi Alexandre, > -----Original Message----- > From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com] > Sent: Wednesday, April 20, 2016 4:01 AM > To: Anurag Kumar Vulisha > Cc: Alessandro Zummo ; Soren Brinkmann > ; Michal Simek ; rtc- > linux@googlegroups.com; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; Punnaiah Choudary Kalluri ; > Anirudha Sarangi ; Srikanth Vemula > ; Anurag Kumar Vulisha > Subject: Re: [PATCH 3/3] RTC: Update seconds time programming logic > > > Hi, > > Please use rtc: zynqmp in your subject line. > > On 12/04/2016 at 17:45:46 +0530, Anurag Kumar Vulisha wrote : > > @@ -78,6 +85,17 @@ static int xlnx_rtc_set_time(struct device *dev, > > struct rtc_time *tm) > > > > writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); > > > > + /* > > + * Clear the rtc interrupt status register after setting the > > + * time. During a read_time function, the code should read the > > + * RTC_INT_STATUS register and if bit 0 is still 0, it means > > + * that one second has not elapsed yet since RTC was set and > > + * the current time should be read from SET_TIME_READ register; > > + * otherwise, CURRENT_TIME register is read to report the time > > + */ > > + writel(RTC_INT_SEC | RTC_INT_ALRM, xrtcdev->reg_base + > RTC_INT_STS); > > You probably shouldn't clear RTC_INT_ALRM here but it should be done in > the init and when enabling/disabling alarm. Or maybe easier would be to > ignore RTC_INT_ALRM in xlnx_rtc_interrupt when it is not set in > RTC_INT_MASK. > Thanks for reviewing the patch. I will remove this clearing RTC_INT_ALRM interrupt logic and send the next version of the patch. > Or, instead of using interrupts, can't you simply read RTC_INT_STS in > xlnx_rtc_read_time()? Is it updated even when the interrupt is not enabled? > The reason for me keeping this logic is, our RTC controller updates the read register after 1 sec delay, so when read , it gives 1 sec delay(correct time - 1 sec). So to avoid that we are programming load time + 1sec into the write register. So when read we would be getting the correct time without any delay. If any request comes from user to read time before RTC updating the read register, we need to give the previous loaded time instead of giving the time from the read register. For doing the above said, we are relaying on seconds interrupt in RTC_INT_STS register. We Clear the RTC_INT_STS register while programming the time into the write register . If we get a request from user to read time within the 1 sec period i.e before the RTC_INT_SEC interrupt bit is set in RTC_INT_STS, we need to give the previous loaded time. This should be done if time is requested from user space within 1 sec period after writing time, after the 1 sec delay if user requested the time , we can give the give time from read register . This is because the correct time is being updated in the read register after 1 sec delay. For this logic to happen we are depending on xrtcdev->time_updated variable to get updated after the very fist RTC_INT_SEC interrupt occurance in the interrupt handler. Since we are relaying on xrtcdev->time_updated to get updated from interrupt handler, I think reading the RTC_INT_STS in xlnx_rtc_read_time() is not helpful. Thanks, Anurag Kumar V > > + xrtcdev->time_updated = 0; > > + > > return 0; > > } > > > > @@ -85,7 +103,17 @@ static int xlnx_rtc_read_time(struct device *dev, > > struct rtc_time *tm) { > > struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); > > > > - rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm); > > + if (xrtcdev->time_updated == 0) { > > + /* > > + * Time written in SET_TIME_WRITE has not yet updated into > > + * the seconds read register, so read the time from the > > + * SET_TIME_WRITE instead of CURRENT_TIME register. > > + */ > > + rtc_time64_to_tm(readl(xrtcdev->reg_base + > RTC_SET_TM_RD), tm); > > + tm->tm_sec -= 1; > > + } else { > > + rtc_time64_to_tm(readl(xrtcdev->reg_base + > RTC_CUR_TM), tm); > > + } > > > > return rtc_valid_tm(tm); > > } > > @@ -133,6 +161,9 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev > > *xrtcdev) { > > u32 rtc_ctrl; > > > > + /* Enable RTC SEC interrupts */ > > + writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_EN); > > + > > /* Enable RTC switch to battery when VCC_PSAUX is not available */ > > rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); > > rtc_ctrl |= RTC_BATT_EN; > > @@ -169,8 +200,13 @@ static irqreturn_t xlnx_rtc_interrupt(int irq, void > *id) > > /* Clear interrupt */ > > writel(status, xrtcdev->reg_base + RTC_INT_STS); > > > > - if (status & RTC_INT_SEC) > > + if (status & RTC_INT_SEC) { > > + if (xrtcdev->time_updated == 0) { > > + /* RTC updated the seconds read register */ > > + xrtcdev->time_updated = 1; > > + } > > rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_UF); > > + } > > if (status & RTC_INT_ALRM) > > rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF); > > > > -- > > 2.1.2 > > > > -- > Alexandre Belloni, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com