Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933208AbcDTKbS (ORCPT ); Wed, 20 Apr 2016 06:31:18 -0400 Received: from mail-cys01nam02on0067.outbound.protection.outlook.com ([104.47.37.67]:13151 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932188AbcDTKbO convert rfc822-to-8bit (ORCPT ); Wed, 20 Apr 2016 06:31:14 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Anurag Kumar Vulisha To: Alexandre Belloni CC: Alessandro Zummo , Soren Brinkmann , Michal Simek , "rtc-linux@googlegroups.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Punnaiah Choudary Kalluri , Anirudha Sarangi , Srikanth Vemula , Srinivas Goud Subject: RE: [PATCH 3/3] RTC: Update seconds time programming logic Thread-Topic: [PATCH 3/3] RTC: Update seconds time programming logic Thread-Index: AQHRlLUSCjpso4UInESpOuGO8Xkd/Z+RZtCAgAENi8D//5C/gIAAoQDQ Date: Wed, 20 Apr 2016 10:31:06 +0000 Message-ID: <3802E9A6666DF54886E2B9CBF743BA9825E0B4BE@XAP-PVEXMBX01.xlnx.xilinx.com> References: <1460463346-24923-1-git-send-email-anuragku@xilinx.com> <1460463346-24923-3-git-send-email-anuragku@xilinx.com> <20160419223109.GF29844@piout.net> <3802E9A6666DF54886E2B9CBF743BA9825E0B42B@XAP-PVEXMBX01.xlnx.xilinx.com> <20160420075741.GK29844@piout.net> In-Reply-To: <20160420075741.GK29844@piout.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.97.204] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22272.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(377454003)(13464003)(55846006)(5890100001)(15975445007)(106466001)(3846002)(5250100002)(15650500001)(586003)(23726003)(5008740100001)(6806005)(93886004)(4001430100002)(92566002)(81166005)(2420400007)(2900100001)(110136002)(106116001)(102836003)(50466002)(50986999)(5003600100002)(4326007)(2906002)(1220700001)(54356999)(87936001)(46406003)(63266004)(10710500007)(6116002)(97756001)(1096002)(86362001)(19580395003)(107886002)(19580405001)(11100500001)(2950100001)(76176999)(189998001)(2920100001)(33656002)(16601075003)(5004730100002)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT053;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 2c29660b-c818-4324-421a-08d36906e4ce X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT053; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521026)(601004)(2401047)(13023025)(13017025)(5005006)(8121501046)(13024025)(13015025)(13018025)(3002001)(10201501046);SRVR:CY1NAM02HT053;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT053; X-Forefront-PRVS: 0918748D70 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2016 10:31:11.5064 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT053 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 6480 Lines: 141 Hi Alexandre, > -----Original Message----- > From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com] > Sent: Wednesday, April 20, 2016 1:28 PM > To: Anurag Kumar Vulisha > Cc: Alessandro Zummo ; Soren Brinkmann > ; Michal Simek ; rtc- > linux@googlegroups.com; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; Punnaiah Choudary Kalluri ; > Anirudha Sarangi ; Srikanth Vemula > ; Srinivas Goud > Subject: Re: [PATCH 3/3] RTC: Update seconds time programming logic > > On 20/04/2016 at 07:10:22 +0000, Anurag Kumar Vulisha wrote : > > The reason for me keeping this logic is, our RTC controller updates > > the read register after 1 sec delay, so when read , it gives 1 sec > > delay(correct time - 1 sec). So to avoid that we are programming load > > time + 1sec into the write register. So when read we would be getting > > the correct time without any delay. If any request comes from user to read > time before RTC updating the read register, we need to give the previous > loaded time instead of giving the time from the read register. > > For doing the above said, we are relaying on seconds interrupt in > > RTC_INT_STS register. We Clear the RTC_INT_STS register while > > programming the time into the write register . If we get a request > > from user to read time within the 1 sec period i.e before the RTC_INT_SEC > interrupt bit is set in RTC_INT_STS, we need to give the previous loaded > time. > > This should be done if time is requested from user space within 1 sec > > period after writing time, after the 1 sec delay if user requested > > the time , we can give the give time from read register . This is > > because the correct time is being updated in the read register after 1 > > sec delay. For this logic to happen we are depending on xrtcdev- > >time_updated variable to get updated after the very fist RTC_INT_SEC > interrupt occurance in the interrupt handler. > > Since we are relaying on xrtcdev->time_updated to get updated from > > interrupt handler, I think reading the RTC_INT_STS in xlnx_rtc_read_time() > is not helpful. > > > > Yeas, I understood that. But my question was whether the interrupt handling > was necessary at all. > Instead of waiting for an interrupt to set time_updated, can't you simply read > RTC_INT_STS and check for the RTC_INT_SEC bit in > xlnx_rtc_read_time() ? > > Something like: > > status = readl(xrtcdev->reg_base + RTC_INT_STS) if (status & RTC_INT_SEC) > rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm); > else > rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1, > tm); > > It all depends on whether the RTC_INT_SEC bit in RTC_INT_STS is being > updated even when it is not enabled as an interrupt. > The above said logic will work if we doesn't clear the RTC_INT_STS register after the RTC_INT_SEC bit is set, this happens only if interrupts are not enabled. If interrupts are enabled we will be clearing the RTC_INT_STS every time in the interrupt handler. And moreover we need to return time from RTC_SET_TM_RD only if time is requested within 1 sec span after programming the time only , so this is required only for one time. Since we are clearing the RTC_INT_STS in our interrupt handler, we might end up in giving the wrong time to the user when requested.So I think this logic might not work. Please correct me if am wrong. Thanks, Anurag Kumar V > > Thanks, > > Anurag Kumar V > > > > > > + xrtcdev->time_updated = 0; > > > > + > > > > return 0; > > > > } > > > > > > > > @@ -85,7 +103,17 @@ static int xlnx_rtc_read_time(struct device > > > > *dev, struct rtc_time *tm) { > > > > struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); > > > > > > > > - rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm); > > > > + if (xrtcdev->time_updated == 0) { > > > > + /* > > > > + * Time written in SET_TIME_WRITE has not yet updated into > > > > + * the seconds read register, so read the time from the > > > > + * SET_TIME_WRITE instead of CURRENT_TIME register. > > > > + */ > > > > + rtc_time64_to_tm(readl(xrtcdev->reg_base + > > > RTC_SET_TM_RD), tm); > > > > + tm->tm_sec -= 1; > > > > + } else { > > > > + rtc_time64_to_tm(readl(xrtcdev->reg_base + > > > RTC_CUR_TM), tm); > > > > + } > > > > > > > > return rtc_valid_tm(tm); > > > > } > > > > @@ -133,6 +161,9 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev > > > > *xrtcdev) { > > > > u32 rtc_ctrl; > > > > > > > > + /* Enable RTC SEC interrupts */ > > > > + writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_EN); > > > > + > > > > /* Enable RTC switch to battery when VCC_PSAUX is not available */ > > > > rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); > > > > rtc_ctrl |= RTC_BATT_EN; > > > > @@ -169,8 +200,13 @@ static irqreturn_t xlnx_rtc_interrupt(int > > > > irq, void > > > *id) > > > > /* Clear interrupt */ > > > > writel(status, xrtcdev->reg_base + RTC_INT_STS); > > > > > > > > - if (status & RTC_INT_SEC) > > > > + if (status & RTC_INT_SEC) { > > > > + if (xrtcdev->time_updated == 0) { > > > > + /* RTC updated the seconds read register */ > > > > + xrtcdev->time_updated = 1; > > > > + } > > > > rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_UF); > > > > + } > > > > if (status & RTC_INT_ALRM) > > > > rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF); > > > > > > > > -- > > > > 2.1.2 > > > > > > > > > > -- > > > Alexandre Belloni, Free Electrons > > > Embedded Linux, Kernel and Android engineering > > > http://free-electrons.com > > -- > Alexandre Belloni, Free Electrons > Embedded Linux, Kernel and Android engineering http://free-electrons.com This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. 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