Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752120AbcDUKjq (ORCPT ); Thu, 21 Apr 2016 06:39:46 -0400 Received: from mail-sn1nam02on0079.outbound.protection.outlook.com ([104.47.36.79]:52928 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751836AbcDUKi4 (ORCPT ); Thu, 21 Apr 2016 06:38:56 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Kedareswara rao Appana To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v3 1/3] dmaengine: vdma: Add config structure to differentiate dmas Date: Thu, 21 Apr 2016 16:08:36 +0530 Message-ID: <1461235118-800-2-git-send-email-appanad@xilinx.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1461235118-800-1-git-send-email-appanad@xilinx.com> References: <1461235118-800-1-git-send-email-appanad@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22274.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(50466002)(90966002)(2201001)(6806005)(92566002)(87936001)(47776003)(50986999)(229853001)(106466001)(86362001)(81166005)(76176999)(33646002)(189998001)(5008740100001)(48376002)(5001770100001)(63266004)(50226001)(52956003)(42186005)(2950100001)(1220700001)(11100500001)(5003940100001)(2906002)(1096002)(19580395003)(586003)(19580405001)(36756003)(4001450100002)(103686003)(46386002)(4326007)(45336002)(107986001)(921003)(2101003)(83996005)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT242;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:sfv;MX:1;A:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 09226070-11d2-4cc2-7a79-08d369d122b3 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT242; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521045)(601004)(2401047)(13018025)(13015025)(13024025)(13023025)(13017025)(8121501046)(5005006)(3002001)(10201501046);SRVR:BL2NAM02HT242;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT242; X-Forefront-PRVS: 091949432C X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2016 10:38:53.7338 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT242 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 10207 Lines: 264 This patch adds config structure in the driver to differentiate AXI DMA's and to add more features(clock support etc..) to these DMA's. Signed-off-by: Kedareswara rao Appana --- Changes for v3: ---> New patch. drivers/dma/xilinx/xilinx_vdma.c | 81 +++++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 31 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c index 70caea6..5bfaa32 100644 --- a/drivers/dma/xilinx/xilinx_vdma.c +++ b/drivers/dma/xilinx/xilinx_vdma.c @@ -342,6 +342,10 @@ struct xilinx_dma_chan { void (*start_transfer)(struct xilinx_dma_chan *chan); }; +struct dma_config { + enum xdma_ip_type dmatype; +}; + /** * struct xilinx_dma_device - DMA device structure * @regs: I/O mapped base address @@ -361,7 +365,7 @@ struct xilinx_dma_device { bool has_sg; u32 flush_on_fsync; bool ext_addr; - enum xdma_ip_type dmatype; + const struct dma_config *dma_config; }; /* Macros */ @@ -573,12 +577,12 @@ xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, if (!desc) return; - if (chan->xdev->dmatype == XDMA_TYPE_VDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { list_for_each_entry_safe(segment, next, &desc->segments, node) { list_del(&segment->node); xilinx_vdma_free_tx_segment(chan, segment); } - } else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) { + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { list_for_each_entry_safe(cdma_segment, cdma_next, &desc->segments, node) { list_del(&cdma_segment->node); @@ -641,7 +645,7 @@ static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) dev_dbg(chan->dev, "Free all channel resources.\n"); xilinx_dma_free_descriptors(chan); - if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) xilinx_dma_free_tx_segment(chan, chan->seg_v); dma_pool_destroy(chan->desc_pool); chan->desc_pool = NULL; @@ -711,13 +715,13 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) * We need the descriptor to be aligned to 64bytes * for meeting Xilinx VDMA specification requirement. */ - if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { chan->desc_pool = dma_pool_create("xilinx_dma_desc_pool", chan->dev, sizeof(struct xilinx_axidma_tx_segment), __alignof__(struct xilinx_axidma_tx_segment), 0); - } else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) { + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", chan->dev, sizeof(struct xilinx_cdma_tx_segment), @@ -738,7 +742,7 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) return -ENOMEM; } - if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) /* * For AXI DMA case after submitting a pending_list, keep * an extra segment allocated so that the "next descriptor" @@ -751,7 +755,7 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) dma_cookie_init(dchan); - if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { /* For AXI DMA resetting once channel will reset the * other channel as well so enable the interrupts here. */ @@ -759,7 +763,7 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) XILINX_DMA_DMAXR_ALL_IRQ_MASK); } - if ((chan->xdev->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) + if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_CDMA_CR_SGMODE); @@ -790,7 +794,7 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, if (ret == DMA_COMPLETE || !txstate) return ret; - if (chan->xdev->dmatype == XDMA_TYPE_AXIDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { spin_lock_irqsave(&chan->lock, flags); desc = list_last_entry(&chan->active_list, @@ -1332,12 +1336,12 @@ static void append_desc_queue(struct xilinx_dma_chan *chan, */ tail_desc = list_last_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); - if (chan->xdev->dmatype == XDMA_TYPE_VDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); tail_segment->hw.next_desc = (u32)desc->async_tx.phys; - } else if (chan->xdev->dmatype == XDMA_TYPE_CDMA) { + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { cdma_tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_cdma_tx_segment, node); @@ -1357,8 +1361,8 @@ append: list_add_tail(&desc->node, &chan->pending_list); chan->desc_pendingcount++; - if (chan->has_sg && (chan->xdev->dmatype == XDMA_TYPE_VDMA) && - unlikely(chan->desc_pendingcount > chan->num_frms)) { + if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) + && unlikely(chan->desc_pendingcount > chan->num_frms)) { dev_dbg(chan->dev, "desc pendingcount is too high\n"); chan->desc_pendingcount = chan->num_frms; } @@ -1811,7 +1815,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->id = 0; chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; - if (xdev->dmatype == XDMA_TYPE_VDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || @@ -1824,7 +1828,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->id = 1; chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; - if (xdev->dmatype == XDMA_TYPE_VDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || @@ -1845,9 +1849,9 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, return err; } - if (xdev->dmatype == XDMA_TYPE_AXIDMA) + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) chan->start_transfer = xilinx_dma_start_transfer; - else if (xdev->dmatype == XDMA_TYPE_CDMA) + else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) chan->start_transfer = xilinx_cdma_start_transfer; else chan->start_transfer = xilinx_vdma_start_transfer; @@ -1894,13 +1898,22 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, return dma_get_slave_channel(&xdev->chan[chan_id]->common); } +static const struct dma_config axidma_config = { + .dmatype = XDMA_TYPE_AXIDMA, +}; + +static const struct dma_config axicdma_config = { + .dmatype = XDMA_TYPE_CDMA, +}; + +static const struct dma_config axivdma_config = { + .dmatype = XDMA_TYPE_VDMA, +}; + static const struct of_device_id xilinx_dma_of_ids[] = { - { .compatible = "xlnx,axi-dma-1.00.a", - .data = (void *)XDMA_TYPE_AXIDMA }, - { .compatible = "xlnx,axi-cdma-1.00.a", - .data = (void *)XDMA_TYPE_CDMA }, - { .compatible = "xlnx,axi-vdma-1.00.a", - .data = (void *)XDMA_TYPE_VDMA }, + { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, + { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, + { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, {} }; MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); @@ -1915,7 +1928,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; struct xilinx_dma_device *xdev; - struct device_node *child; + struct device_node *child, *np = pdev->dev.of_node; struct resource *io; u32 num_frames, addr_width; int i, err; @@ -1926,7 +1939,13 @@ static int xilinx_dma_probe(struct platform_device *pdev) return -ENOMEM; xdev->dev = &pdev->dev; - xdev->dmatype = (enum xdma_ip_type)of_device_get_match_data(&pdev->dev); + if (np) { + const struct of_device_id *match; + + match = of_match_node(xilinx_dma_of_ids, np); + if (match && match->data) + xdev->dma_config = match->data; + } /* Request and map I/O memory */ io = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1937,7 +1956,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) /* Retrieve the DMA engine properties from the device tree */ xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); - if (xdev->dmatype == XDMA_TYPE_VDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores", &num_frames); if (err < 0) { @@ -1969,7 +1988,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) xdev->common.dev = &pdev->dev; INIT_LIST_HEAD(&xdev->common.channels); - if (!(xdev->dmatype == XDMA_TYPE_CDMA)) { + if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); } @@ -1981,12 +2000,12 @@ static int xilinx_dma_probe(struct platform_device *pdev) xdev->common.device_terminate_all = xilinx_dma_terminate_all; xdev->common.device_tx_status = xilinx_dma_tx_status; xdev->common.device_issue_pending = xilinx_dma_issue_pending; - if (xdev->dmatype == XDMA_TYPE_AXIDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; /* Residue calculation is supported by only AXI DMA */ xdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; - } else if (xdev->dmatype == XDMA_TYPE_CDMA) { + } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; } else { @@ -2003,7 +2022,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) goto error; } - if (xdev->dmatype == XDMA_TYPE_VDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) if (xdev->chan[i]) xdev->chan[i]->num_frms = num_frames; -- 2.1.2