Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752009AbcDUK6T (ORCPT ); Thu, 21 Apr 2016 06:58:19 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:37939 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751887AbcDUK6R (ORCPT ); Thu, 21 Apr 2016 06:58:17 -0400 Subject: Re: [RESEND PATCH 0/3 v6] Add Mediatek MT8173 cpufreq driver To: Daniel Kurtz References: <1439803465-19683-1-git-send-email-pi-cheng.chen@linaro.org> <20150826021659.GD8784@linux> <22538895.vrRgZUmQTV@vostro.rjw.lan> <55E73077.8060106@gmail.com> <5718AAF0.3010606@gmail.com> Cc: Pi-Cheng Chen , Viresh Kumar , Mark Rutland , "Rafael J. Wysocki" , Michael Turquette , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Linux Kernel Mailing List , "linux-pm@vger.kernel.org" , Linaro Kernel Mailman List , linux-mediatek@lists.infradead.org From: Matthias Brugger Message-ID: <5718B244.3020201@gmail.com> Date: Thu, 21 Apr 2016 12:58:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.0 MIME-Version: 1.0 In-Reply-To: <5718AAF0.3010606@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1694 Lines: 56 On 21/04/16 12:26, Matthias Brugger wrote: > > > On 02/09/15 19:23, Matthias Brugger wrote: >> >> >> On 02/09/15 08:45, Daniel Kurtz wrote: >>> Matthias, >>> >>> On Fri, Aug 28, 2015 at 10:06 PM, Rafael J. Wysocki >>> wrote: >>>> On Wednesday, August 26, 2015 02:53:39 PM Pi-Cheng Chen wrote: >>>>> On Wed, Aug 26, 2015 at 10:16 AM, Viresh Kumar >>>>> wrote: >>>>>> On 26-08-15, 09:25, Pi-Cheng Chen wrote: >>>>>>> The [3/3] is based on Mediatek SoC maintainer tree[1] and the >>>>>>> patch which >>>>>>> introduce a new clock type[2] consumed by MT8173 cpufreq driver. >>>>>>> So it will >>>>>>> cause some conflicts if it goes through your tree. I am not sure >>>>>>> how this >>>>>>> should be handled, but should it be merged through Mediatek SoC >>>>>>> maintainer >>>>>>> tree? >>>>>> >>>>>> Just get that applied to MTK tree, it doesn't have any dependency on >>>>>> rest of the patches for build/boot. The only thing is that cpufreq >>>>>> wouldn't work and it will work as soon as Rafael's and MTK's trees >>>>>> are >>>>>> merged by Linus. >>>>> >>>>> Thanks for your explanation. >>>>> >>>>> @Rafael, Would you please apply [1,2] to your tree? >>>> >>>> Applied, thanks! >>> >>> Can you please apply [3] from this set to your dts tree? >>> >> >> I will as soon as v4.3-rc1 shows up. > > I somehow forgot this patch. Sorry for that. > Applied for v4.6-next/dts64 right now. > I just realized that CLK_INFRA_CA53SEL and CLK_APMIXED_MAINPLL are not part of the clk driver. Pi-Cheng, can you check if they got renamed in the meanwhile? Or do we need some clock driver patches that enable this clocks for the series? Regards, Matthias