Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752093AbcDULEp (ORCPT ); Thu, 21 Apr 2016 07:04:45 -0400 Received: from mail-wm0-f42.google.com ([74.125.82.42]:37549 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751770AbcDULEn (ORCPT ); Thu, 21 Apr 2016 07:04:43 -0400 From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com, vinod.koul@intel.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, broonie@kernel.org, ludovic.barre@st.com Subject: [PATCH 01/18] dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation Date: Thu, 21 Apr 2016 12:04:18 +0100 Message-Id: <1461236675-10176-2-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461236675-10176-1-git-send-email-peter.griffin@linaro.org> References: <1461236675-10176-1-git-send-email-peter.griffin@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3415 Lines: 105 This patch adds the DT binding documentation for the FDMA constroller found on STi based chipsets from STMicroelectronics. Signed-off-by: Ludovic Barre Signed-off-by: Peter Griffin --- Documentation/devicetree/bindings/dma/st_fdma.txt | 87 +++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/st_fdma.txt diff --git a/Documentation/devicetree/bindings/dma/st_fdma.txt b/Documentation/devicetree/bindings/dma/st_fdma.txt new file mode 100644 index 0000000..13029dc --- /dev/null +++ b/Documentation/devicetree/bindings/dma/st_fdma.txt @@ -0,0 +1,87 @@ +* STMicroelectronics Flexible Direct Memory Access Device Tree bindings + +The FDMA is a general-purpose direct memory access controller capable of +supporting 16 independent DMA channels. It accepts up to 32 DMA requests. +The FDMA is based on a Slim processor which require a firmware. + +* FDMA Controller + +Required properties: +- compatible : Should be one of + - st,stih407-fdma-mpe31-11 + - st,stih407-fdma-mpe31-12 + - st,stih407-fdma-mpe31-13 +- reg : Should contain DMA registers location and length +- interrupts : Should contain one interrupt shared by all channels +- dma-channels : Number of channels supported by the controller +- #dma-cells : Must be <3>. See DMA client section below +- clocks : Must contain an entry for each name in clock-names +- clock-names : Must contain "fdma_slim, fdma_hi, fdma_low, fdma_ic" entries +See: Documentation/devicetree/bindings/clock/clock-bindings.txt + + +Example: + + fdma1-app: dma-controller@8e40000 { + compatible = "st,stih407-fdma-mpe31-11"; + reg = <0x8e40000 0x20000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + clocks = <&CLK_S_C0_FLEXGEN CLK_FDMA>, + <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>, + <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>, + <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>; + clock-names = "fdma_slim", + "fdma_hi", + "fdma_low", + "fdma_ic"; + }; + +* DMA client + +Required properties: +- dmas: Comma separated list of dma channel requests +- dma-names: Names of the aforementioned requested channels + +Each dmas request consists of 4 cells: +1. A phandle pointing to the FDMA controller +2. The request line number +3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h) + -bit 2-0: Holdoff value, dreq will be masked for + 0x0: 0-0.5us + 0x1: 0.5-1us + 0x2: 1-1.5us + -bit 17: data swap + 0x0: disabled + 0x1: enabled + -bit 21: Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 22: 2 STBus Initiator Coprocessor interface + 0x0: high priority port + 0x1: low priority port +4. transfers type + 0 free running + 1 paced + +Example: + + sti_uni_player2: sti-uni-player@2 { + compatible = "st,sti-uni-player"; + status = "disabled"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clock-parents = <&clk_s_d0_quadfs 2>; + assigned-clock-rates = <50000000>; + reg = <0x8D82000 0x158>; + interrupts = ; + dmas = <&fdma0 4 0 1>; + dai-name = "Uni Player #1 (DAC)"; + dma-names = "tx"; + st,uniperiph-id = <2>; + st,version = <5>; + st,mode = "PCM"; + }; -- 1.9.1