Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752249AbcDUNIL (ORCPT ); Thu, 21 Apr 2016 09:08:11 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:20820 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751968AbcDUNIJ (ORCPT ); Thu, 21 Apr 2016 09:08:09 -0400 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , "stable # v3 . 10" , "Maciej W. Rozycki" , , James Hogan , "Markos Chandras" Subject: [PATCH 11/11] MIPS: math-emu: Fix jalr emulation when rd == $0 Date: Thu, 21 Apr 2016 14:04:55 +0100 Message-ID: <1461243895-30371-12-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1461243895-30371-1-git-send-email-paul.burton@imgtec.com> References: <1461243895-30371-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.100.200.79] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1381 Lines: 38 When emulating a jalr instruction with rd == $0, the code in isBranchInstr was incorrectly writing to GPR $0 which should actually always remain zeroed. This would lead to any further instructions emulated which use $0 operating on a bogus value until the task is next context switched, at which point the value of $0 in the task context would be restored to the correct zero by a store in SAVE_SOME. Fix this by not writing to rd if it is $0. Fixes: 102cedc32a6e ("MIPS: microMIPS: Floating point support.") Cc: stable # v3.10 Signed-off-by: Paul Burton --- arch/mips/math-emu/cp1emu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 85dd174..d96e912 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -445,9 +445,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, case spec_op: switch (insn.r_format.func) { case jalr_op: - regs->regs[insn.r_format.rd] = - regs->cp0_epc + dec_insn.pc_inc + - dec_insn.next_pc_inc; + if (insn.r_format.rd != 0) { + regs->regs[insn.r_format.rd] = + regs->cp0_epc + dec_insn.pc_inc + + dec_insn.next_pc_inc; + } /* Fall through */ case jr_op: /* For R6, JR already emulated in jalr_op */ -- 2.8.0