Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753214AbcDVBud (ORCPT ); Thu, 21 Apr 2016 21:50:33 -0400 Received: from regular1.263xmail.com ([211.150.99.130]:47933 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751594AbcDVBub (ORCPT ); Thu, 21 Apr 2016 21:50:31 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-KSVirus-check: 0 X-RL-SENDER: jay.xu@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: jay.xu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs To: Marc Zyngier , =?UTF-8?Q?Heiko_St=c3=bcbner?= References: <1461122150-9042-1-git-send-email-jay.xu@rock-chips.com> <5718AFB8.5070004@rock-chips.com> <20160421123018.096d4a75@arm.com> <2131452.5tyGOfVRfi@diego> <20160421221228.359fab3c@arm.com> Cc: "Huang, Tao" , Mark Rutland , will.deacon@arm.com, robh+dt@kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, catalin.marinas@arm.com, davidriley@chromium.org, dianders@chromium.org, jwerner@chromium.org, smbarber@chromium.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: "jay.xu" Message-ID: <57198351.2060608@rock-chips.com> Date: Fri, 22 Apr 2016 09:50:09 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20160421221228.359fab3c@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2967 Lines: 85 Hi Marc: On 2016年04月22日 05:12, Marc Zyngier wrote: > On Thu, 21 Apr 2016 22:24:09 +0200 > Heiko Stübner wrote: > >> Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier: >>> On Thu, 21 Apr 2016 18:47:20 +0800 >>> >>> "Huang, Tao" wrote: >>>> Hi, Mark: >>>> >>>> On 2016年04月21日 18:19, Mark Rutland wrote: >>>>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote: >>>>>> + cpu_l0: cpu@0 { >>>>>> + device_type = "cpu"; >>>>>> + compatible = "arm,cortex-a53", "arm,armv8"; >>>>>> + reg = <0x0 0x0>; >>>>>> + enable-method = "psci"; >>>>>> + #cooling-cells = <2>; /* min followed by max */ >>>>>> + clocks = <&cru ARMCLKL>; >>>>>> + }; >>>>>> + cpu_b0: cpu@100 { >>>>>> + device_type = "cpu"; >>>>>> + compatible = "arm,cortex-a72", "arm,armv8"; >>>>>> + reg = <0x0 0x100>; >>>>>> + enable-method = "psci"; >>>>>> + #cooling-cells = <2>; /* min followed by max */ >>>>>> + clocks = <&cru ARMCLKB>; >>>>>> + }; >>>>>> + >>>>>> + arm-pmu { >>>>>> + compatible = "arm,armv8-pmuv3"; >>>>>> + interrupts = ; >>>>>> + }; >>>>> This is wrong, and must go. There should be a separate node for the PMU >>>>> of each microarchitecture, with the appropriate compatible string to >>>>> represent that (see the juno dts). >>>> You are right. The first version we wrote is: >>>> pmu_a53 { >>>> >>>> compatible = "arm,cortex-a53-pmu"; >>>> interrupts = ; >>>> interrupt-affinity = <&cpu_l0>, >>>> >>>> <&cpu_l1>, >>>> <&cpu_l2>, >>>> <&cpu_l3>; >>>> >>>> }; >>>> >>>> pmu_a72 { >>>> >>>> compatible = "arm,cortex-a72-pmu"; >>>> interrupts = ; >>>> interrupt-affinity = <&cpu_b0>, >>>> >>>> <&cpu_b1>; >>>> >>>> }; >>>> >>>> but unfortunately, the arm pmu driver do not support PPI in two cluster >>>> well, >>>> so we have to replace with this implementation. >>>> >>>>> In this case things are messier as the same PPI number is being used >>>>> across clusters. Marc (Cc'd) has been working on PPI partitions, which >>>>> should allow us to support that. >>>> Great! So what we can do right now? Wait this feature, and delete >>>> arm-pmu node? >>> I'd rather you have a look at the patches, test them with your HW, >>> and comment on what doesn't work! >> I would think we could do it in two tracks, testing and fixing but also letting >> the rk3399 devicetrees move forward without the pmu at first :-) . > Where would the fun be then? ;-) thanks for your advices, and I will try to test the percpu-partition patches. by the way, do you think it's better to let the dtsi be reviewed first, then the percpu-partition patches could be tested by more people ? Jianqun > > M.