Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752163AbcDVGOO (ORCPT ); Fri, 22 Apr 2016 02:14:14 -0400 Received: from mail-sn1nam02on0076.outbound.protection.outlook.com ([104.47.36.76]:16530 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751659AbcDVGOI (ORCPT ); Fri, 22 Apr 2016 02:14:08 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Kedareswara rao Appana To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH v4 3/3] dmaengine: vdma: Add clock support Date: Fri, 22 Apr 2016 11:43:50 +0530 Message-ID: <1461305630-4826-4-git-send-email-appanad@xilinx.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1461305630-4826-1-git-send-email-appanad@xilinx.com> References: <1461305630-4826-1-git-send-email-appanad@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22274.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(36756003)(90966002)(50466002)(103686003)(63266004)(19580405001)(50986999)(42186005)(229853001)(48376002)(6806005)(106466001)(45336002)(4001450100002)(76176999)(586003)(4326007)(11100500001)(87936001)(19580395003)(1220700001)(2950100001)(47776003)(5008740100001)(1096002)(81166005)(52956003)(46386002)(86362001)(189998001)(2906002)(5001770100001)(50226001)(5003940100001)(92566002)(33646002)(2201001)(36386004)(921003)(107986001)(83996005)(2101003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT227;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:nov;MX:1;A:1;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 6e6d88d3-2a5f-4117-2640-08d36a754ecb X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT227; X-Microsoft-Antispam-PRVS: <2322f9b471294ef68de9891d0d4bf814@SN1NAM02HT227.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521053)(601004)(2401047)(13018025)(13015025)(13024025)(5005006)(13023025)(13017025)(8121501046)(3002001)(10201501046);SRVR:SN1NAM02HT227;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT227; X-Forefront-PRVS: 0920602B08 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2016 06:14:04.9088 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT227 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 9423 Lines: 344 Added basic clock support for axi dma's. The clocks are requested at probe and released at remove. Reviewed-by: Shubhrajyoti Datta Signed-off-by: Kedareswara rao Appana --- Changes for v4: ---> Documented struct members as suggested by Soren. ---> Fixed required clock according to binding but a failure is ignored in the cdma case as suggested by Soren. ---> Removed unnecessary IS_ERR checks during disabling the clocks. Changes for v3: ---> Added clock support for all the AXI DMA's. ---> Fixed clk_unprepare leak during probe fail as suggested by Moritz. ---> Fixed comment driver specifically asks for the clocks it needs and return an error if a mandatory clock is missing as suggested by soren. Changes for v2: ---> None. drivers/dma/xilinx/xilinx_vdma.c | 226 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 224 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c index 255cdca..51c633f 100644 --- a/drivers/dma/xilinx/xilinx_vdma.c +++ b/drivers/dma/xilinx/xilinx_vdma.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "../dmaengine.h" @@ -344,6 +345,9 @@ struct xilinx_dma_chan { struct dma_config { enum xdma_ip_type dmatype; + int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, + struct clk **tx_clk, struct clk **txs_clk, + struct clk **rx_clk, struct clk **rxs_clk); }; /** @@ -355,7 +359,13 @@ struct dma_config { * @has_sg: Specifies whether Scatter-Gather is present or not * @flush_on_fsync: Flush on frame sync * @ext_addr: Indicates 64 bit addressing is supported by dma device + * @pdev: Platform device structure pointer * @dma_config: DMA config structure + * @axi_clk: DMA Axi4-lite interace clock + * @tx_clk: DMA mm2s clock + * @txs_clk: DMA mm2s stream clock + * @rx_clk: DMA s2mm clock + * @rxs_clk: DMA s2mm stream clock */ struct xilinx_dma_device { void __iomem *regs; @@ -365,7 +375,13 @@ struct xilinx_dma_device { bool has_sg; u32 flush_on_fsync; bool ext_addr; + struct platform_device *pdev; const struct dma_config *dma_config; + struct clk *axi_clk; + struct clk *tx_clk; + struct clk *txs_clk; + struct clk *rx_clk; + struct clk *rxs_clk; }; /* Macros */ @@ -1757,6 +1773,195 @@ static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) list_del(&chan->common.device_node); } +static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, + struct clk **tx_clk, struct clk **rx_clk, + struct clk **sg_clk, struct clk **tmp_clk) +{ + int err; + + *tmp_clk = NULL; + + *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); + if (IS_ERR(*axi_clk)) { + err = PTR_ERR(*axi_clk); + dev_err(&pdev->dev, "failed to get axi_aclk (%u)\n", err); + return err; + } + + *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); + if (IS_ERR(*tx_clk)) + *tx_clk = NULL; + + *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); + if (IS_ERR(*rx_clk)) + *rx_clk = NULL; + + *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); + if (IS_ERR(*sg_clk)) + *sg_clk = NULL; + + err = clk_prepare_enable(*axi_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err); + return err; + } + + err = clk_prepare_enable(*tx_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); + goto err_disable_axiclk; + } + + err = clk_prepare_enable(*rx_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err); + goto err_disable_txclk; + } + + err = clk_prepare_enable(*sg_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable sg_clk (%u)\n", err); + goto err_disable_rxclk; + } + + return 0; + +err_disable_rxclk: + clk_disable_unprepare(*rx_clk); +err_disable_txclk: + clk_disable_unprepare(*tx_clk); +err_disable_axiclk: + clk_disable_unprepare(*axi_clk); + + return err; +} + +static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, + struct clk **dev_clk, struct clk **tmp_clk, + struct clk **tmp1_clk, struct clk **tmp2_clk) +{ + int err; + + *tmp_clk = NULL; + *tmp1_clk = NULL; + *tmp2_clk = NULL; + + *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); + if (IS_ERR(*axi_clk)) { + err = PTR_ERR(*axi_clk); + dev_err(&pdev->dev, "failed to get axi_clk (%u)\n", err); + return err; + } + + *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); + if (IS_ERR(*dev_clk)) { + err = PTR_ERR(*dev_clk); + dev_err(&pdev->dev, "failed to get dev_clk (%u)\n", err); + return err; + } + + err = clk_prepare_enable(*axi_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err); + return err; + } + + err = clk_prepare_enable(*dev_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable dev_clk (%u)\n", err); + goto err_disable_axiclk; + } + + return 0; + +err_disable_axiclk: + clk_disable_unprepare(*axi_clk); + + return err; +} + +static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, + struct clk **tx_clk, struct clk **txs_clk, + struct clk **rx_clk, struct clk **rxs_clk) +{ + int err; + + *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); + if (IS_ERR(*axi_clk)) { + err = PTR_ERR(*axi_clk); + dev_err(&pdev->dev, "failed to get axi_aclk (%u)\n", err); + return err; + } + + *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); + if (IS_ERR(*tx_clk)) + *tx_clk = NULL; + + *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); + if (IS_ERR(*txs_clk)) + *txs_clk = NULL; + + *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); + if (IS_ERR(*rx_clk)) + *rx_clk = NULL; + + *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); + if (IS_ERR(*rxs_clk)) + *rxs_clk = NULL; + + err = clk_prepare_enable(*axi_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable axi_clk (%u)\n", err); + return err; + } + + err = clk_prepare_enable(*tx_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); + goto err_disable_axiclk; + } + + err = clk_prepare_enable(*txs_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable txs_clk (%u)\n", err); + goto err_disable_txclk; + } + + err = clk_prepare_enable(*rx_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err); + goto err_disable_txsclk; + } + + err = clk_prepare_enable(*rxs_clk); + if (err) { + dev_err(&pdev->dev, "failed to enable rxs_clk (%u)\n", err); + goto err_disable_rxclk; + } + + return 0; + +err_disable_rxclk: + clk_disable_unprepare(*rx_clk); +err_disable_txsclk: + clk_disable_unprepare(*txs_clk); +err_disable_txclk: + clk_disable_unprepare(*tx_clk); +err_disable_axiclk: + clk_disable_unprepare(*axi_clk); + + return err; +} + +static void xdma_disable_allclks(struct xilinx_dma_device *xdev) +{ + clk_disable_unprepare(xdev->rxs_clk); + clk_disable_unprepare(xdev->rx_clk); + clk_disable_unprepare(xdev->txs_clk); + clk_disable_unprepare(xdev->tx_clk); + clk_disable_unprepare(xdev->axi_clk); +} + /** * xilinx_dma_chan_probe - Per Channel Probing * It get channel features from the device tree entry and @@ -1900,14 +2105,17 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, static const struct dma_config axidma_config = { .dmatype = XDMA_TYPE_AXIDMA, + .clk_init = axidma_clk_init, }; static const struct dma_config axicdma_config = { .dmatype = XDMA_TYPE_CDMA, + .clk_init = axicdma_clk_init, }; static const struct dma_config axivdma_config = { .dmatype = XDMA_TYPE_VDMA, + .clk_init = axivdma_clk_init, }; static const struct of_device_id xilinx_dma_of_ids[] = { @@ -1926,6 +2134,9 @@ MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); */ static int xilinx_dma_probe(struct platform_device *pdev) { + int (*clk_init)(struct platform_device *, struct clk **, struct clk **, + struct clk **, struct clk **, struct clk **) + = axivdma_clk_init; struct device_node *node = pdev->dev.of_node; struct xilinx_dma_device *xdev; struct device_node *child, *np = pdev->dev.of_node; @@ -1943,10 +2154,17 @@ static int xilinx_dma_probe(struct platform_device *pdev) const struct of_device_id *match; match = of_match_node(xilinx_dma_of_ids, np); - if (match && match->data) + if (match && match->data) { xdev->dma_config = match->data; + clk_init = xdev->dma_config->clk_init; + } } + err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, + &xdev->rx_clk, &xdev->rxs_clk); + if (err) + return err; + /* Request and map I/O memory */ io = platform_get_resource(pdev, IORESOURCE_MEM, 0); xdev->regs = devm_ioremap_resource(&pdev->dev, io); @@ -2019,7 +2237,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) for_each_child_of_node(node, child) { err = xilinx_dma_chan_probe(xdev, child); if (err < 0) - goto error; + goto disable_clks; } if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ -2043,6 +2261,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) return 0; +disable_clks: + xdma_disable_allclks(xdev); error: for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++) if (xdev->chan[i]) @@ -2070,6 +2290,8 @@ static int xilinx_dma_remove(struct platform_device *pdev) if (xdev->chan[i]) xilinx_dma_chan_remove(xdev->chan[i]); + xdma_disable_allclks(xdev); + return 0; } -- 2.1.2