Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752070AbcDVKb5 (ORCPT ); Fri, 22 Apr 2016 06:31:57 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5870 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751172AbcDVKby (ORCPT ); Fri, 22 Apr 2016 06:31:54 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 22 Apr 2016 03:31:42 -0700 From: Penny Chiu To: , , , , , , CC: , , , , , , , , "Penny Chiu" Subject: [PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Date: Fri, 22 Apr 2016 18:31:00 +0800 Message-ID: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> X-Mailer: git-send-email 2.8.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2465 Lines: 48 This patch series implements the DFLL/CL-DVFS clock source on Tegra210 based on Tegra124 DFLL driver, Tegra210 support on Tegra124 cpufreq driver, and exposes DFLL HW as a PWM controller and provides DFLL_PWM driver to generate PWM signals to control an OpenVReg (PWM regulator) for CPU rail. This patch series has been tested on the Jetson TX1. Penny Chiu (11): clk: tegra: dfll: Fix voltage comparison clk: tegra: dfll: Move SoC specific data into of_device_id clk: tegra: Add DFLL DVCO reset control for Tegra210 clk: tegra: Add Tegra210 support in DFLL driver pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller clk: tegra: dfll: Add PWM inferface cpufreq: tegra124: Add Tegra210 support arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 arm64: tegra: Add DFLL clock node on Jetson TX1 arm64: tegra: Add clock properties on cpu0 for Tegra210 arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator .../bindings/clock/nvidia,tegra124-dfll.txt | 21 +- .../bindings/pwm/nvidia,tegra-dfll-pwm.txt | 48 +++ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 56 +++ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 23 ++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 21 + arch/arm64/configs/defconfig | 4 + drivers/clk/tegra/Makefile | 4 +- drivers/clk/tegra/clk-dfll.c | 422 +++++++++++++++------ drivers/clk/tegra/clk-dfll.h | 1 + drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 127 ++++++- drivers/clk/tegra/clk-tegra210.c | 68 ++++ drivers/clk/tegra/cvb.c | 12 +- drivers/clk/tegra/cvb.h | 8 +- drivers/cpufreq/tegra124-cpufreq.c | 3 +- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-tegra-dfll.c | 322 ++++++++++++++++ include/dt-bindings/reset/tegra210-car.h | 12 + include/soc/tegra/pwm-tegra-dfll.h | 27 ++ 19 files changed, 1046 insertions(+), 144 deletions(-) create mode 100644 Documentation/devicetree/bindings/pwm/nvidia,tegra-dfll-pwm.txt create mode 100644 drivers/pwm/pwm-tegra-dfll.c create mode 100644 include/dt-bindings/reset/tegra210-car.h create mode 100644 include/soc/tegra/pwm-tegra-dfll.h -- 2.8.1