Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753032AbcDVKcs (ORCPT ); Fri, 22 Apr 2016 06:32:48 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5955 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752891AbcDVKcp (ORCPT ); Fri, 22 Apr 2016 06:32:45 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 22 Apr 2016 03:32:35 -0700 From: Penny Chiu To: , , , , , , CC: , , , , , , , , Penny Chiu Subject: [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Date: Fri, 22 Apr 2016 18:31:10 +0800 Message-ID: <1461321071-6431-11-git-send-email-pchiu@nvidia.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> References: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 819 Lines: 27 Add clocks, clock-names, and clock-latency into cpu0 node. These properties will be used by cpufreq driver. Signed-off-by: Penny Chiu --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 204d9cd..1a85857 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -782,6 +782,12 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; }; cpu@1 { -- 2.8.1