Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754228AbcDVLNI (ORCPT ); Fri, 22 Apr 2016 07:13:08 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8770 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752429AbcDVLNE (ORCPT ); Fri, 22 Apr 2016 07:13:04 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 22 Apr 2016 04:12:53 -0700 Subject: Re: [PATCH V2 13/14] dt-bindings: arm-gic: Add documentation for Tegra210 AGIC To: Mark Rutland References: <1461150237-15580-1-git-send-email-jonathanh@nvidia.com> <1461150237-15580-14-git-send-email-jonathanh@nvidia.com> <20160422100052.GA10606@leverpostej> CC: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Pawel Moll , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , , , From: Jon Hunter Message-ID: <571A0739.3090502@nvidia.com> Date: Fri, 22 Apr 2016 12:12:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <20160422100052.GA10606@leverpostej> X-Originating-IP: [10.21.132.108] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1986 Lines: 54 On 22/04/16 11:00, Mark Rutland wrote: > On Wed, Apr 20, 2016 at 12:03:56PM +0100, Jon Hunter wrote: >> The Tegra AGIC interrupt controller is compatible with the ARM GIC-400 >> interrupt controller. > > The cover letter says it _is_ a GIC-400, just used in a slightly unusual > manner (i.e. not directly connected to CPUs). Correct. >> The Tegra AGIC requires two clocks, namely the >> "ape" (functional) and "apb2ape" (interface) clocks, to operate. Add >> the compatible string and clock information for the AGIC to the GIC >> device-tree binding documentation. > > The GIC-400 spec only describes "CLK" (which is what I imagine "ape" is. > There isn't an APB clock described, and the manual seems to show GIC-400 > directly connected to AXI rather than APB, so that doesn't seem to even > be the usual "apb_pclk". > > Is there some wrapper logic around a GIC-400 to giove it an APB > interface? Or am I misudnerstanding the spec? Looking at the Tegra documentation what we have is ... APB --> AXI switch --> AGIC (GIC400) I am not sure how such a switch would typically be modeled in DT but we need the apb clock to interface to the GIC registers. I am not sure if something like simple-pm-bus is appropriate here. >> Signed-off-by: Jon Hunter >> --- >> >> I am not sure if it will be popular to add Tegra specific clock names >> to the GIC DT docs. However, in that case, then possibly the only >> alternative is to move the Tegra AGIC driver into its own file and >> expose the GIC APIs for it to use. Then we could add our own DT doc >> for the Tegra AGIC as well (based upon the ARM GIC). > > The clock-names don't seem right to me, as they sound like provide names > or global clock line names rather than consumer-side names ("clk" and > "apb_pclk"). Yes that would be fine with me. > I'm also not certain about the compatible string; if this really is a > GIC-400 then I would at least expect "arm,gic-400" as a fallback. OK. Cheers Jon