Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751683AbcDWFiI (ORCPT ); Sat, 23 Apr 2016 01:38:08 -0400 Received: from mail-sn1nam02on0056.outbound.protection.outlook.com ([104.47.36.56]:56704 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750757AbcDWFiF convert rfc822-to-8bit (ORCPT ); Sat, 23 Apr 2016 01:38:05 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Appana Durga Kedareswara Rao To: Rob Herring CC: "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , Michal Simek , Soren Brinkmann , "vinod.koul@intel.com" , "dan.j.williams@intel.com" , "moritz.fischer@ettus.com" , "laurent.pinchart@ideasonboard.com" , "luis@debethencourt.com" , Anirudha Sarangi , Punnaiah Choudary Kalluri , Shubhrajyoti Datta , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "dmaengine@vger.kernel.org" Subject: RE: [PATCH v2 1/2] Documentation: DT: vdma: Add clock support for vdma Thread-Topic: [PATCH v2 1/2] Documentation: DT: vdma: Add clock support for vdma Thread-Index: AQHRmvnjaqEeUdQ9Z0mAPFDNwlseoZ+V4KWAgAEteyA= Date: Sat, 23 Apr 2016 05:37:57 +0000 Message-ID: References: <1461152599-28858-1-git-send-email-appanad@xilinx.com> <20160422193707.GA16116@rob-hp-laptop> In-Reply-To: <20160422193707.GA16116@rob-hp-laptop> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.229.118] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22276.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(13464003)(377454003)(189002)(24454002)(199003)(76176999)(2950100001)(2906002)(92566002)(63266004)(47776003)(102836003)(87936001)(5008740100001)(11100500001)(86362001)(5003600100002)(5004730100002)(189998001)(2920100001)(2900100001)(5250100002)(33656002)(106116001)(6806005)(110136002)(50466002)(19580395003)(97756001)(586003)(23726003)(106466001)(81166005)(55846006)(6116002)(1096002)(19580405001)(46406003)(54356999)(1220700001)(4326007)(50986999)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT047;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:sfv;MX:1;A:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 734669d6-7403-4188-1cb2-08d36b396f99 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT047; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521062)(601004)(2401047)(13018025)(13017025)(8121501046)(5005006)(13015025)(13024025)(13023025)(3002001)(10201501046)(6055026);SRVR:CY1NAM02HT047;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT047; X-Forefront-PRVS: 0921D55E4F X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2016 05:38:01.0860 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT047 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2644 Lines: 66 Hi Rob, Thanks for the review... > -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Saturday, April 23, 2016 1:07 AM > To: Appana Durga Kedareswara Rao > Cc: pawel.moll@arm.com; mark.rutland@arm.com; > ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek > ; Soren Brinkmann ; > vinod.koul@intel.com; dan.j.williams@intel.com; Appana Durga Kedareswara > Rao ; moritz.fischer@ettus.com; > laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha > Sarangi ; Punnaiah Choudary Kalluri > ; Shubhrajyoti Datta ; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; dmaengine@vger.kernel.org > Subject: Re: [PATCH v2 1/2] Documentation: DT: vdma: Add clock support for > vdma > > On Wed, Apr 20, 2016 at 05:13:18PM +0530, Kedareswara rao Appana wrote: > > This patch updates the binding doc with clock description for vdma. > > > > Signed-off-by: Kedareswara rao Appana > > --- > > Changes for v2: > > --> Listed down all the clocks supported by the h/w > > as suggested by the Datta. > > --> Used IP clock names instead of shortcut clock names. > > > > Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | 8 > > ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt > > b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt > > index fcc2b65..afe9eb7 100644 > > --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt > > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt > > @@ -21,6 +21,11 @@ Required properties: > > - dma-channel child node: Should have at least one channel and can have up > to > > two channels per device. This node specifies the properties of each > > DMA channel (see child node properties below). > > +- clocks: Input clock specifier. Refer to common clock bindings. > > +- clock-names: List of input clocks "s_axi_lite_aclk", "m_axi_mm2s_aclk" > > + "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" > > + (list of input cloks may vary based on the ip configuration. > > s/cloks/clocks/ > > > + see clock bindings for more info). > > This does not make sense. The common clock binding is going to tell me more > about how the clocks vary? I have fixed these comments in the other version (v4) you acked that patch... Regards, Kedar. > > You need to define here how the clocks can vary.