Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752144AbcDWMz4 (ORCPT ); Sat, 23 Apr 2016 08:55:56 -0400 Received: from terminus.zytor.com ([198.137.202.10]:39242 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751609AbcDWMzy (ORCPT ); Sat, 23 Apr 2016 08:55:54 -0400 Date: Sat, 23 Apr 2016 05:55:11 -0700 From: tip-bot for Kan Liang Message-ID: Cc: hpa@zytor.com, mingo@kernel.org, acme@redhat.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, vincent.weaver@maine.edu, tglx@linutronix.de, alexander.shishkin@linux.intel.com, jolsa@redhat.com, kan.liang@intel.com, peterz@infradead.org, eranian@google.com Reply-To: peterz@infradead.org, eranian@google.com, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, vincent.weaver@maine.edu, hpa@zytor.com, acme@redhat.com, mingo@kernel.org, alexander.shishkin@linux.intel.com, jolsa@redhat.com, kan.liang@intel.com, tglx@linutronix.de In-Reply-To: <1460706825-46163-1-git-send-email-kan.liang@intel.com> References: <1460706825-46163-1-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs Git-Commit-ID: f21d5adceb7f2660e5227569faed278f6fb2072e X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2914 Lines: 85 Commit-ID: f21d5adceb7f2660e5227569faed278f6fb2072e Gitweb: http://git.kernel.org/tip/f21d5adceb7f2660e5227569faed278f6fb2072e Author: Kan Liang AuthorDate: Fri, 15 Apr 2016 00:53:45 -0700 Committer: Ingo Molnar CommitDate: Sat, 23 Apr 2016 14:12:31 +0200 perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs LBR filtering is also supported on the Silvermont and Airmont microarchitectures. The layout of MSR_LBR_SELECT is the same as Nehalem. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1460706825-46163-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 2 +- arch/x86/events/intel/lbr.c | 18 ++++++++++++++++++ arch/x86/events/perf_event.h | 2 ++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 92fda6b..79b5943 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3581,7 +3581,7 @@ __init int intel_pmu_init(void) memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); - intel_pmu_lbr_init_atom(); + intel_pmu_lbr_init_slm(); x86_pmu.event_constraints = intel_slm_event_constraints; x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index ad26ca7..317e29e 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1058,6 +1058,24 @@ void __init intel_pmu_lbr_init_atom(void) pr_cont("8-deep LBR, "); } +/* slm */ +void __init intel_pmu_lbr_init_slm(void) +{ + x86_pmu.lbr_nr = 8; + x86_pmu.lbr_tos = MSR_LBR_TOS; + x86_pmu.lbr_from = MSR_LBR_CORE_FROM; + x86_pmu.lbr_to = MSR_LBR_CORE_TO; + + x86_pmu.lbr_sel_mask = LBR_SEL_MASK; + x86_pmu.lbr_sel_map = nhm_lbr_sel_map; + + /* + * SW branch filter usage: + * - compensate for lack of HW filter + */ + pr_cont("8-deep LBR, "); +} + /* Knights Landing */ void intel_pmu_lbr_init_knl(void) { diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 8b78481..7d62a02 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -909,6 +909,8 @@ void intel_pmu_lbr_init_nhm(void); void intel_pmu_lbr_init_atom(void); +void intel_pmu_lbr_init_slm(void); + void intel_pmu_lbr_init_snb(void); void intel_pmu_lbr_init_hsw(void);