Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933301AbcDYRsO (ORCPT ); Mon, 25 Apr 2016 13:48:14 -0400 Received: from mail-by2on0057.outbound.protection.outlook.com ([207.46.100.57]:10911 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754915AbcDYRsH (ORCPT ); Mon, 25 Apr 2016 13:48:07 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=pass (signature was verified) header.d=altera.onmicrosoft.com;vger.kernel.org; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: alien8.de; dkim=none (message not signed) header.d=none;alien8.de; dmarc=none action=none header.from=opensource.altera.com; From: To: , , , , , , , , , , CC: , , , , , , Subject: [PATCHv2 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support Date: Mon, 25 Apr 2016 12:52:47 -0500 Message-ID: <1461606768-14404-7-git-send-email-tthayer@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1461606768-14404-1-git-send-email-tthayer@opensource.altera.com> References: <1461606768-14404-1-git-send-email-tthayer@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BLUPR05CA0052.namprd05.prod.outlook.com (10.141.20.22) To BLUPR03MB1476.namprd03.prod.outlook.com (10.163.81.18) X-MS-Office365-Filtering-Correlation-Id: 8571a5f8-49a8-49ea-2dec-08d36d31bc4e X-Microsoft-Exchange-Diagnostics-untrusted: 1;BLUPR03MB1476;2:h7G2RDI8zJnn6cfulenyRIyjeDIm0gVWbt7w6z+YSiPGKPi191nzL7i84eh+dV0WR7evxF0VscBufJRbITZyZFKAEWPYNq9WWMgvMWhjMYxpUJW2Aqo/NXF8XKxxqp7/a0V/6NyFBr0rT6BqA8O91JmGkgDhjUOxy0HAr7ggNSxKI+WkfYpmfgHF8UU9rYVg;3:fDjEqopSEAwz9LOCaL2te0J0DIeNk2QesuOmm4DOATdGXfEGduuZygK+mMSajgcem4Wxca3g2RvzsJh5dOJTawr1eZSezqzCmB5ttz/hX9m/wOzyuPq8dVin3XznvnKC;25:bqPOFhWcHjnIdfV06CNBWMDJEn3gt+L2HADPq0ngGpOVWeVbyF6KuFu4hFX23/kihYrMqLYGO2ZuqXZEJz73qxSvNN0frFu5SGnl4+kmCEnIbe54hTKYAewYMd4Cx/IDWfYiwCh2hLm5athsj0qTmqey/0RwS2acwcho8k7FKofxCpB8rpuaTAwjeDVRIO5c1aBXDny+OTP8DurKJwwcMnkyiZgCHQXUKTN9m57SMs1zrJhMwpwy7Ee2wvVysIlisRqBXsYSU8ZG3atWsCLcDRXvmIMDbOGcz4oflD6Xtz60wRqNmsKu+Ckwi055JVN39LhzDbaNCveLcXtm9+r/fQ==;20:+OG/WIpbPhSC5n0yPN7XHpsgi7zljEbEAYtZ8kwfB0waAeyU0z/3jgO8f200hqy8NymrjZag1ZD0WapnWJwfkABey9rTYyWM4pM15RvK6l+CFVzeS0jOxoBHkDVap6qzL/5MlZ4H1U8PjpCf8qXmKl8l75aHqS8PFMDlL7knvHo= X-Microsoft-Antispam-Untrusted: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB1476; 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Signed-off-by: Thor Thayer --- v2 Remove (void *) cast from altr_edac_device_of_match[] Addition of panic flag to private data. --- drivers/edac/Kconfig | 7 ++ drivers/edac/altera_edac.c | 159 ++++++++++++++++++++++++++++++++++++++++++++ drivers/edac/altera_edac.h | 14 ++++ 3 files changed, 180 insertions(+) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 6ca7474..d0c1dab 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM Support for error detection and correction on the Altera On-Chip RAM Memory for Altera SoCs. +config EDAC_ALTERA_ETHERNET + bool "Altera Ethernet FIFO ECC" + depends on EDAC_ALTERA=y + help + Support for error detection and correction on the + Altera Ethernet FIFO Memory for Altera SoCs. + config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" depends on EDAC_MM_EDAC && ARCH_ZYNQ diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 49a5239..3860880 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -553,6 +553,12 @@ const struct edac_device_prv_data ocramecc_data; const struct edac_device_prv_data l2ecc_data; const struct edac_device_prv_data a10_ocramecc_data; const struct edac_device_prv_data a10_l2ecc_data; +const struct edac_device_prv_data a10_enet0rxecc_data; +const struct edac_device_prv_data a10_enet0txecc_data; +const struct edac_device_prv_data a10_enet1rxecc_data; +const struct edac_device_prv_data a10_enet1txecc_data; +const struct edac_device_prv_data a10_enet2rxecc_data; +const struct edac_device_prv_data a10_enet2txecc_data; static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) { @@ -693,6 +699,20 @@ static const struct of_device_id altr_edac_device_of_match[] = { { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, { .compatible = "altr,socfpga-a10-ocram-ecc", .data = &a10_ocramecc_data }, #endif +#ifdef CONFIG_EDAC_ALTERA_ETHERNET + { .compatible = "altr,socfpga-a10-emac0-rx-ecc", + .data = &a10_enet0rxecc_data }, + { .compatible = "altr,socfpga-a10-emac0-tx-ecc", + .data = &a10_enet0txecc_data }, + { .compatible = "altr,socfpga-a10-emac1-rx-ecc", + .data = &a10_enet1rxecc_data }, + { .compatible = "altr,socfpga-a10-emac1-tx-ecc", + .data = &a10_enet1txecc_data }, + { .compatible = "altr,socfpga-a10-emac2-rx-ecc", + .data = &a10_enet2rxecc_data }, + { .compatible = "altr,socfpga-a10-emac2-tx-ecc", + .data = &a10_enet2txecc_data }, +#endif {}, }; MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); @@ -1205,6 +1225,132 @@ const struct edac_device_prv_data a10_l2ecc_data = { #endif /* CONFIG_EDAC_ALTERA_L2C */ +/********************* Ethernet Device Functions ********************/ + +#ifdef CONFIG_EDAC_ALTERA_ETHERNET + +const struct edac_device_prv_data a10_enet0rxecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_EMAC0RX, + .dbgfs_name = "altr_emac0rx_trigger", + .ecc_enable_mask = ALTR_A10_ETHERNET_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, + .panic = false, +}; + +const struct edac_device_prv_data a10_enet0txecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_EMAC0TX, + .dbgfs_name = "altr_emac0tx_trigger", + .ecc_enable_mask = ALTR_A10_ETHERNET_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, + .panic = false, +}; + +const struct edac_device_prv_data a10_enet1rxecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_EMAC1RX, + .dbgfs_name = "altr_emac1rx_trigger", + .ecc_enable_mask = ALTR_A10_ETHERNET_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, + .panic = false, +}; + +const struct edac_device_prv_data a10_enet1txecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_EMAC1TX, + .dbgfs_name = "altr_emac1tx_trigger", + .ecc_enable_mask = ALTR_A10_ETHERNET_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, + .panic = false, +}; + +const struct edac_device_prv_data a10_enet2rxecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_EMAC2RX, + .dbgfs_name = "altr_emac2rx_trigger", + .ecc_enable_mask = ALTR_A10_ETHERNET_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, + .panic = false, +}; + +const struct edac_device_prv_data a10_enet2txecc_data = { + .setup = altr_check_ecc_deps, + .ce_clear_mask = ALTR_A10_ECC_SERRPENA, + .ue_clear_mask = ALTR_A10_ECC_DERRPENA, + .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_EMAC2TX, + .dbgfs_name = "altr_emac2tx_trigger", + .ecc_enable_mask = ALTR_A10_ETHERNET_ECC_EN_CTL, + .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, + .ce_set_mask = ALTR_A10_ECC_TSERRA, + .ue_set_mask = ALTR_A10_ECC_TDERRA, + .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, + .ecc_irq_handler = altr_edac_a10_ecc_irq, + .inject_fops = &altr_edac_a10_device_inject_fops, + .panic = false, +}; + +static const struct a10_ecc_init_vars a10_enet_ecc_init[] = { + {"altr,socfpga-a10-emac0-rx-ecc", A10_SYSMGR_ECC_INTSTAT_EMAC0RX}, + {"altr,socfpga-a10-emac0-tx-ecc", A10_SYSMGR_ECC_INTSTAT_EMAC0TX}, + {"altr,socfpga-a10-emac1-rx-ecc", A10_SYSMGR_ECC_INTSTAT_EMAC1RX}, + {"altr,socfpga-a10-emac1-tx-ecc", A10_SYSMGR_ECC_INTSTAT_EMAC1TX}, + {"altr,socfpga-a10-emac2-rx-ecc", A10_SYSMGR_ECC_INTSTAT_EMAC2RX}, + {"altr,socfpga-a10-emac2-tx-ecc", A10_SYSMGR_ECC_INTSTAT_EMAC2TX}, +}; + +static int __init socfpga_init_ethernet_ecc(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(a10_enet_ecc_init); i++) { + altr_init_a10_ecc_block(a10_enet_ecc_init[i].ecc_str, + a10_enet_ecc_init[i].irq_mask, + ALTR_A10_ETHERNET_ECC_EN_CTL, 0); + } + + return 0; +} + +early_initcall(socfpga_init_ethernet_ecc); + +#endif /* CONFIG_EDAC_ALTERA_ETHERNET */ + /********************* Arria10 EDAC Device Functions *************************/ /* @@ -1416,6 +1562,19 @@ static int altr_edac_a10_probe(struct platform_device *pdev) else if (of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc")) altr_edac_a10_device_add(edac, child); + else if ((of_device_is_compatible(child, + "altr,socfpga-a10-emac0-rx-ecc")) || + (of_device_is_compatible(child, + "altr,socfpga-a10-emac0-tx-ecc")) || + (of_device_is_compatible(child, + "altr,socfpga-a10-emac1-rx-ecc")) || + (of_device_is_compatible(child, + "altr,socfpga-a10-emac1-tx-ecc")) || + (of_device_is_compatible(child, + "altr,socfpga-a10-emac2-rx-ecc")) || + (of_device_is_compatible(child, + "altr,socfpga-a10-emac2-tx-ecc"))) + altr_edac_a10_device_add(edac, child); } return 0; diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h index a4f1539..fa0fe19 100644 --- a/drivers/edac/altera_edac.h +++ b/drivers/edac/altera_edac.h @@ -260,6 +260,12 @@ struct altr_sdram_mc_data { #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0 #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0) #define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1) +#define A10_SYSMGR_ECC_INTSTAT_EMAC0RX BIT(4) +#define A10_SYSMGR_ECC_INTSTAT_EMAC0TX BIT(5) +#define A10_SYSMGR_ECC_INTSTAT_EMAC1RX BIT(6) +#define A10_SYSMGR_ECC_INTSTAT_EMAC1TX BIT(7) +#define A10_SYSMGR_ECC_INTSTAT_EMAC2RX BIT(8) +#define A10_SYSMGR_ECC_INTSTAT_EMAC2TX BIT(9) #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8 #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15) @@ -285,6 +291,9 @@ struct altr_sdram_mc_data { /* Arria 10 OCRAM ECC Management Group Defines */ #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0)) +/* Arria 10 Ethernet ECC Management Group Defines */ +#define ALTR_A10_ETHERNET_ECC_EN_CTL BIT(0) + /* A10 ECC Controller memory initialization timeout */ #define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000 @@ -332,4 +341,9 @@ struct altr_arria10_edac { struct list_head a10_ecc_devices; }; +struct a10_ecc_init_vars { + u8 ecc_str[32]; + u32 irq_mask; +}; + #endif /* #ifndef _ALTERA_EDAC_H */ -- 1.7.9.5