Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753142AbcD0LWE (ORCPT ); Wed, 27 Apr 2016 07:22:04 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:37836 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751866AbcD0LWA (ORCPT ); Wed, 27 Apr 2016 07:22:00 -0400 Subject: Re: [PATCH 1/3] DRA7: Fix clock data for gmac_gmii_ref_clk_div To: "J.D. Schroeder" , , , , , , , , , , , , References: <1461693269-19436-1-git-send-email-Linux.HWI@garmin.com> <1461693269-19436-2-git-send-email-Linux.HWI@garmin.com> CC: "J.D. Schroeder" From: Tero Kristo Message-ID: <5720A09F.2060701@ti.com> Date: Wed, 27 Apr 2016 14:21:03 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1461693269-19436-2-git-send-email-Linux.HWI@garmin.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2399 Lines: 63 On 26/04/16 20:54, J.D. Schroeder wrote: > From: "J.D. Schroeder" > > This commit fixes the clock data inside the DRA7xx clocks device tree > structure for the gmac_gmii_ref_clk_div clock. This clock is actually > the GMAC_MAIN_CLK and has nothing to do with the register at address > 0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is > set to 1 in order to use the GMAC_RMII_CLK instead of the > GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > > By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to > have the parent of dpll_gmac_m2_ck always divided by 2 the warning is > resolved and the clock tree is fixed up. > > Additionally, a new clock called rmii_50mhz_clk_mux is defined that > does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the > source clock for the RMII_50MHZ_CLK. > > Signed-off-by: J.D. Schroeder > Reviewed-by: Trenton Andres Looks like something weird happened with the clock data conversion tool with this specific clock. Seems to be the only buggy instance in our clock data across SoCs. Good catch. Acked-by: Tero Kristo > --- > arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi > index d0bae06..9d1a583 100644 > --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi > +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi > @@ -1710,13 +1710,20 @@ > reg = <0x0c00>; > }; > > - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { > + rmii_50mhz_clk_mux: rmii_50mhz_clk_mux { > #clock-cells = <0>; > - compatible = "ti,divider-clock"; > - clocks = <&dpll_gmac_m2_ck>; > + compatible = "ti,mux-clock"; > + clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; > ti,bit-shift = <24>; > reg = <0x13d0>; > - ti,dividers = <2>; > + }; > + > + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { > + #clock-cells = <0>; > + compatible = "fixed-factor-clock"; > + clocks = <&dpll_gmac_m2_ck>; > + clock-mult = <1>; > + clock-div = <2>; > }; > > gmac_rft_clk_mux: gmac_rft_clk_mux { >