Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753137AbcD0NsZ (ORCPT ); Wed, 27 Apr 2016 09:48:25 -0400 Received: from mga09.intel.com ([134.134.136.24]:28178 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752205AbcD0NsW (ORCPT ); Wed, 27 Apr 2016 09:48:22 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,541,1455004800"; d="scan'208";a="793495104" From: Andy Shevchenko To: "Bryan O'Donoghue" , Peter Hurley , linux-serial@vger.kernel.org, Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Greg Kroah-Hartman , ismo.puustinen@intel.com, Heikki Krogerus Cc: Andy Shevchenko Subject: [PATCH v3 03/11] dmaengine: dw: set polarity of handshake interface Date: Wed, 27 Apr 2016 16:48:06 +0300 Message-Id: <1461764894-14891-4-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1461764894-14891-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1461764894-14891-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1655 Lines: 48 Intel Quark UART uses DesignWare DMA IP. Though the DMA IP is connected in such way that handshake interface uses inverted polarity. We have to provide a possibility to set this in the DMA driver when configuring a channel. Introduce a new member of custom slave configuration called 'polarity' and set active low polarity in case this value is 'true'. Signed-off-by: Andy Shevchenko --- drivers/dma/dw/core.c | 2 ++ include/linux/platform_data/dma-dw.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 81b06df..9c7bc7a 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -150,6 +150,8 @@ static void dwc_initialize(struct dw_dma_chan *dwc) cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); + cfglo |= dwc->dws.polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; + channel_writel(dwc, CFG_LO, cfglo); channel_writel(dwc, CFG_HI, cfghi); diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index d15d8ba..192f3a2 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -23,6 +23,7 @@ * @dst_id: dst request line * @m_master: memory master for transfers on allocated channel * @p_master: peripheral master for transfers on allocated channel + * @polarity: set active low polarity of handshake interface */ struct dw_dma_slave { struct device *dma_dev; @@ -30,6 +31,7 @@ struct dw_dma_slave { u8 dst_id; u8 m_master; u8 p_master; + bool polarity; }; /** -- 2.8.0.rc3