Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753308AbcD0POR (ORCPT ); Wed, 27 Apr 2016 11:14:17 -0400 Received: from mail-oi0-f46.google.com ([209.85.218.46]:34664 "EHLO mail-oi0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753241AbcD0POM (ORCPT ); Wed, 27 Apr 2016 11:14:12 -0400 MIME-Version: 1.0 In-Reply-To: <5720D546.6050105@amd.com> References: <20160426225553.13567.19459.stgit@tlendack-t1.amdoffice.net> <20160426225604.13567.55443.stgit@tlendack-t1.amdoffice.net> <5720D066.7080409@amd.com> <5720D546.6050105@amd.com> From: Andy Lutomirski Date: Wed, 27 Apr 2016 08:12:56 -0700 Message-ID: Subject: Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors To: Tom Lendacky Cc: linux-arch , "linux-efi@vger.kernel.org" , kvm list , "linux-doc@vger.kernel.org" , X86 ML , "linux-kernel@vger.kernel.org" , kasan-dev , "linux-mm@kvack.org" , iommu@lists.linux-foundation.org, =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Arnd Bergmann , Jonathan Corbet , Matt Fleming , Joerg Roedel , Konrad Rzeszutek Wilk , Paolo Bonzini , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Andrey Ryabinin , Alexander Potapenko , Thomas Gleixner , Dmitry Vyukov Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1474 Lines: 42 On Wed, Apr 27, 2016 at 8:05 AM, Tom Lendacky wrote: > On 04/27/2016 09:47 AM, Andy Lutomirski wrote: >> On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky wrote: >>> On 04/27/2016 09:33 AM, Andy Lutomirski wrote: >>>> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky wrote: >>>>> For AMD processors that support PAT, set the write-protect cache mode >>>>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >>>> >>>> What's the purpose of using the WP memory type? >>> >>> The WP memory type is used for encrypting or decrypting data "in place". >>> The use of the WP on the source data will prevent any of the source >>> data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in >>> the AMD64 APM link provided in the cover letter. >>> >>> This memory type will be used in subsequent patches for this purpose. >> >> OK. >> >> Why AMD-only? I thought Intel supported WP, too. > > Just me being conservative. If there aren't any objections from the > Intel folks about it we can remove the vendor check and just set it. I think there are some errata that will cause high PAT references to incorrectly reference the low parts of the table, but I don't recall any that go the other way around. So merely setting WP in a high entry should be harmless unless something tries to use it. > > Thanks, > Tom > >> >> --Andy >> -- Andy Lutomirski AMA Capital Management, LLC