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From: Andy Lutomirski <luto@amacapital.net>
Date: Wed, 27 Apr 2016 08:34:42 -0700
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Subject: Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for
 AMD processors
To: Borislav Petkov <bp@alien8.de>
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On Wed, Apr 27, 2016 at 8:31 AM, Borislav Petkov <bp@alien8.de> wrote:
> On Wed, Apr 27, 2016 at 08:12:56AM -0700, Andy Lutomirski wrote:
>> I think there are some errata
>
> Isn't that addressed by the first branch of the if-test in pat_init():
>
>         if ((c->x86_vendor == X86_VENDOR_INTEL) &&
>             (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
>              ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
>

That's the intent, but I'm unconvinced that it's complete.  The reason
that WT is in slot 7 is that if it accidentally ends up using the slot
3 entry instead of 7 (e.g. if a 2M page gets confused due to an
erratum we didn't handle or similar), then it falls back to UC, which
is safe.

But this is mostly moot in this case.  There is no safe fallback for
WP, but it doesn't really matter, because no one will actually try to
use it except on a system will full PAT support anyway.  So I'm not
really concerned.

>
> --
> Regards/Gruss,
>     Boris.
>
> ECO tip #101: Trim your mails when you reply.


-- 
Andy Lutomirski
AMA Capital Management, LLC