Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752705AbcD1K0k (ORCPT ); Thu, 28 Apr 2016 06:26:40 -0400 Received: from terminus.zytor.com ([198.137.202.10]:46878 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751112AbcD1K0i (ORCPT ); Thu, 28 Apr 2016 06:26:38 -0400 Date: Thu, 28 Apr 2016 03:25:55 -0700 From: tip-bot for Kan Liang Message-ID: Cc: jolsa@redhat.com, linux-kernel@vger.kernel.org, tglx@linutronix.de, acme@redhat.com, alexander.shishkin@linux.intel.com, hpa@zytor.com, kan.liang@intel.com, mingo@kernel.org, vincent.weaver@maine.edu, eranian@google.com, peterz@infradead.org Reply-To: alexander.shishkin@linux.intel.com, hpa@zytor.com, jolsa@redhat.com, acme@redhat.com, linux-kernel@vger.kernel.org, tglx@linutronix.de, peterz@infradead.org, eranian@google.com, vincent.weaver@maine.edu, kan.liang@intel.com, mingo@kernel.org In-Reply-To: <1461231010-4399-1-git-send-email-kan.liang@intel.com> References: <1461231010-4399-1-git-send-email-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Fix incorrect lbr_sel_mask value Git-Commit-ID: cf3beb7c90a8efa16a06b26634cddddc92bb819c X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2563 Lines: 62 Commit-ID: cf3beb7c90a8efa16a06b26634cddddc92bb819c Gitweb: http://git.kernel.org/tip/cf3beb7c90a8efa16a06b26634cddddc92bb819c Author: Kan Liang AuthorDate: Thu, 21 Apr 2016 02:30:10 -0700 Committer: Ingo Molnar CommitDate: Thu, 28 Apr 2016 10:32:43 +0200 perf/x86/intel: Fix incorrect lbr_sel_mask value This patch fixes a bug which was introduced by: b16a5b52eb90 ("perf/x86: Add option to disable reading branch flags/cycles") In this patch, lbr_sel_mask is used to mask the lbr_select. But LBR_SEL_MASK doesn't include the bit for LBR_CALL_STACK. So LBR call stack will never be set in lbr_select. This patch corrects the LBR_SEL_MASK by including all valid bits in LBR_SELECT. Also, the LBR_CALL_STACK bit is different as other bit in LBR_SELECT. It does not operate in suppress mode, so it needs to be specially handled in intel_pmu_setup_hw_lbr_filter. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1461231010-4399-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/lbr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 6c3b7c1..1ca5d1e 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -63,7 +63,7 @@ static enum { #define LBR_PLM (LBR_KERNEL | LBR_USER) -#define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */ +#define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */ #define LBR_NOT_SUPP -1 /* LBR filter not supported */ #define LBR_IGN 0 /* ignored */ @@ -610,8 +610,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate * in suppress mode. So LBR_SELECT should be set to * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) + * But the 10th bit LBR_CALL_STACK does not operate + * in suppress mode. */ - reg->config = mask ^ x86_pmu.lbr_sel_mask; + reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) && (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&