Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753218AbcD1JCm (ORCPT ); Thu, 28 Apr 2016 05:02:42 -0400 Received: from mail-bl2nam02on0077.outbound.protection.outlook.com ([104.47.38.77]:21162 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752830AbcD1JCg convert rfc822-to-8bit (ORCPT ); Thu, 28 Apr 2016 05:02:36 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Appana Durga Kedareswara Rao To: Lars-Peter Clausen , "robh+dt@kernel.org" , "pawel.moll@arm.com" , "mark.rutland@arm.com" , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , Michal Simek , Soren Brinkmann , "vinod.koul@intel.com" , "dan.j.williams@intel.com" , "moritz.fischer@ettus.com" , "laurent.pinchart@ideasonboard.com" , "luis@debethencourt.com" , Anirudha Sarangi , "Punnaiah Choudary Kalluri" CC: "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "dmaengine@vger.kernel.org" Subject: RE: [PATCH v7 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Thread-Topic: [PATCH v7 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma device tree binding documentation Thread-Index: AQHRoFND6QhtA/UQr0ONf5+PmTNCA5+c4VsAgACKRoD//9GFgIAB2qfA Date: Thu, 28 Apr 2016 09:00:48 +0000 Message-ID: References: <1461740729-30715-1-git-send-email-appanad@xilinx.com> <57206632.7010508@metafoo.de> <5720B333.4000804@metafoo.de> In-Reply-To: <5720B333.4000804@metafoo.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.95.64] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22288.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(13464003)(377454003)(24454002)(51914003)(87936001)(76176999)(47776003)(2906002)(50986999)(5003600100002)(23726003)(86362001)(106116001)(50466002)(54356999)(106466001)(2900100001)(5250100002)(19580395003)(2501003)(5004730100002)(63266004)(1220700001)(19580405001)(4326007)(1096002)(81166005)(189998001)(551934003)(11100500001)(55846006)(5001770100001)(6806005)(5008740100001)(33656002)(4001450100002)(2920100001)(46406003)(586003)(102836003)(93886004)(3846002)(6116002)(2950100001)(92566002)(2201001)(97756001)(921003)(107986001)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:CY1NAM02HT041;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: cbb3df00-2437-4bb9-1765-08d36f43d2cd X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:CY1NAM02HT041; X-Microsoft-Antispam-PRVS: <697177b74c3d46428544b553e6787684@CY1NAM02HT041.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(9101521072)(601004)(2401047)(13015025)(5005006)(8121501046)(13024025)(13023025)(13018025)(13017025)(10201501046)(3002001)(6055026);SRVR:CY1NAM02HT041;BCL:0;PCL:0;RULEID:;SRVR:CY1NAM02HT041; X-Forefront-PRVS: 0926B0E013 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2016 09:02:27.1082 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT041 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4064 Lines: 87 Hi Lars, Thanks for the review... > -----Original Message----- > From: Lars-Peter Clausen [mailto:lars@metafoo.de] > Sent: Wednesday, April 27, 2016 6:10 PM > To: Appana Durga Kedareswara Rao ; > robh+dt@kernel.org; pawel.moll@arm.com; mark.rutland@arm.com; > ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek > ; Soren Brinkmann ; > vinod.koul@intel.com; dan.j.williams@intel.com; moritz.fischer@ettus.com; > laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha > Sarangi ; Punnaiah Choudary Kalluri > > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; dmaengine@vger.kernel.org > Subject: Re: [PATCH v7 1/2] Documentation: DT: dma: Add Xilinx zynqmp dma > device tree binding documentation > > On 04/27/2016 09:33 AM, Appana Durga Kedareswara Rao wrote: > > Hi Lars, > > > >> -----Original Message----- > >> From: Lars-Peter Clausen [mailto:lars@metafoo.de] > >> Sent: Wednesday, April 27, 2016 12:42 PM > >> To: Appana Durga Kedareswara Rao ; > >> robh+dt@kernel.org; pawel.moll@arm.com; mark.rutland@arm.com; > >> ijc+devicetree@hellion.org.uk; galak@codeaurora.org; Michal Simek > >> ; Soren Brinkmann ; > >> vinod.koul@intel.com; dan.j.williams@intel.com; Appana Durga > >> Kedareswara Rao ; moritz.fischer@ettus.com; > >> laurent.pinchart@ideasonboard.com; luis@debethencourt.com; Anirudha > >> Sarangi ; Punnaiah Choudary Kalluri > >> > >> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > >> linux- kernel@vger.kernel.org; dmaengine@vger.kernel.org > >> Subject: Re: [PATCH v7 1/2] Documentation: DT: dma: Add Xilinx zynqmp > >> dma device tree binding documentation > >> > >> On 04/27/2016 09:05 AM, Kedareswara rao Appana wrote: > >> [...] > >>> +- xlnx,include-sg : Indicates the controller to operate in simple or > >>> + scatter gather dma mode > >>> +- xlnx,ratectrl : Scheduling interval in terms of clock cycles for > >>> + source AXI transaction > >>> +- xlnx,overfetch : Tells whether the channel is allowed to over > >>> + fetch the data > >>> +- xlnx,src-issue : Number of AXI outstanding transactions on source > >> side > >>> +- xlnx,src-burst-len : AXI length for data read. Support only power of > >>> + 2 byte values. > >>> +- xlnx,dst-burst-len : AXI length for data write. Support only power of > >> > >> These are all software runtime configuration parameters that you'd > >> want to change at runtime depending on which peripheral you are > >> targeting with a specific DMA transfer. These really do not belong into the > devicetree. > > > > You mean to have a separate config structure in the driver and handle > > the above parameters Through that structure??? > > > > I understand that above will work for slave dma transfer types what > > about memory to memory Transfers where we don't have provision to the use > this parameters... > > These parameters are just as application specific as e.g. the DMA > source/destination address or the DMA transfer length. If you want to use the > DMA controller in a different configuration you'd have to re-compile the DTB > and reboot your board, that is not really practical. Especially considering that > you'd typically have multiple applications using the DMA controller in different > configurations concurrently. In general if I have to reconfigure the DT depending > on what application software is running something is fundamentally broken. > > Derive these parameters at runtime depending on the requested transfer. E.g. > some transfer types only work in SG mode, others only work in non-SG modes. > For those which can work in both modes choose the one that is more efficient. > Similar for the other parameters. Ok will fix in the next version... Will use module_params for the above properties. Regards, Kedar. > > - Lars