Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753642AbcD1JbY (ORCPT ); Thu, 28 Apr 2016 05:31:24 -0400 Received: from e15.ny.us.ibm.com ([129.33.205.205]:58551 "EHLO e15.ny.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753365AbcD1JbW (ORCPT ); Thu, 28 Apr 2016 05:31:22 -0400 X-IBM-Helo: d01dlp02.pok.ibm.com X-IBM-MailFrom: chandan.kumar@linux.vnet.ibm.com X-IBM-RcptTo: mpe@ellerman.id.au;linuxppc-dev@lists.ozlabs.org;acme@redhat.com;jolsa@redhat.com;linux-kernel@vger.kernel.org From: Chandan Kumar To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: acme@redhat.com, mpe@ellerman.id.au, jolsa@redhat.com, anju@linux.vnet.ibm.com, maddy@linux.vnet.ibm.com, naveen.n.rao@linux.vnet.ibm.com, hemant@linux.vnet.ibm.com Subject: [PATCH 3/3] perf tools: Fix perf regs mask generation Date: Thu, 28 Apr 2016 15:01:10 +0530 Message-Id: <1461835870-67778-4-git-send-email-chandan.kumar@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1461835870-67778-1-git-send-email-chandan.kumar@linux.vnet.ibm.com> References: <1461835870-67778-1-git-send-email-chandan.kumar@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16042809-0037-0000-0000-00002AF42C2E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1175 Lines: 43 From: "Naveen N. Rao" On some architectures (powerpc in particular), the number of registers exceeds what can be represented in an integer bitmask. Ensure we generate the proper bitmask on such platforms. Fixes: 71ad0f5e4 ("perf tools: Support for DWARF CFI unwinding on post processing") Signed-off-by: Naveen N. Rao --- tools/perf/util/perf_regs.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c index 6b8eb13..c4023f2 100644 --- a/tools/perf/util/perf_regs.c +++ b/tools/perf/util/perf_regs.c @@ -12,18 +12,18 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) int i, idx = 0; u64 mask = regs->mask; - if (regs->cache_mask & (1 << id)) + if (regs->cache_mask & (1ULL << id)) goto out; - if (!(mask & (1 << id))) + if (!(mask & (1ULL << id))) return -EINVAL; for (i = 0; i < id; i++) { - if (mask & (1 << i)) + if (mask & (1ULL << i)) idx++; } - regs->cache_mask |= (1 << id); + regs->cache_mask |= (1ULL << id); regs->cache_regs[id] = regs->regs[idx]; out: -- 1.9.3