Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752811AbcD2DlJ (ORCPT ); Thu, 28 Apr 2016 23:41:09 -0400 Received: from mail-ig0-f178.google.com ([209.85.213.178]:36239 "EHLO mail-ig0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752225AbcD2DlH (ORCPT ); Thu, 28 Apr 2016 23:41:07 -0400 MIME-Version: 1.0 In-Reply-To: <1461609378-467-1-git-send-email-caleb@crome.org> References: <1461609378-467-1-git-send-email-caleb@crome.org> Date: Fri, 29 Apr 2016 00:41:05 -0300 Message-ID: Subject: Re: [alsa-devel] [PATCH v2 1/1] ASoC: fsl_ssi: add CCSR_SSI_SOR to volatile register list From: Fabio Estevam To: Caleb Crome Cc: Timur Tabi , Nicolin Chen , Xiubo Li , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , "alsa-devel@alsa-project.org" , "linuxppc-dev@lists.ozlabs.org" , linux-kernel Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1064 Lines: 21 On Mon, Apr 25, 2016 at 3:36 PM, Caleb Crome wrote: > The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo > on the i.MX SSI port. The fsl_ssi_trigger writes this register in > order to clear the fifo at trigger time. > > However, since the CCSR_SSI_SOR register is not in the volatile list, > the caching mechanism prevented the register write in the trigger > function. This caused the fifo to not be cleared (because the value > was unchanged from the last time the register was written), and thus > causes the channels in both TDM or simple I2S mode to slip and be in > the wrong time slots on SSI restart. > > This has gone unnoticed for so long because with simple stereo mode, > the consequence is that left and right are swapped, which isn't that > noticeable. However, it's catestrophic in some systems that > require the channels to be in the right slots. > > Signed-off-by: Caleb Crome > Suggested-by: Arnaud Mouiche Reviewed-by: Fabio Estevam