Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752099AbcJAUdy (ORCPT ); Sat, 1 Oct 2016 16:33:54 -0400 Received: from mail-yb0-f196.google.com ([209.85.213.196]:34672 "EHLO mail-yb0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751100AbcJAUdw (ORCPT ); Sat, 1 Oct 2016 16:33:52 -0400 MIME-Version: 1.0 X-Originating-IP: [212.159.75.221] In-Reply-To: <1475351192-27079-15-git-send-email-Julia.Lawall@lip6.fr> References: <1475351192-27079-1-git-send-email-Julia.Lawall@lip6.fr> <1475351192-27079-15-git-send-email-Julia.Lawall@lip6.fr> From: James Hogan Date: Sat, 1 Oct 2016 21:33:51 +0100 X-Google-Sender-Auth: KaPlNCTNd-Nmu0lRTCGUl_NEGdA Message-ID: Subject: Re: [PATCH 14/15] irqchip/metag-ext: improve function-level documentation To: Julia Lawall Cc: kernel-janitors@vger.kernel.org, Thomas Gleixner , Jason Cooper , Marc Zyngier , metag , LKML Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1173 Lines: 37 Hi Julia, On 1 October 2016 at 20:46, Julia Lawall wrote: > Drop the variable irq which ceased to be a parameter in bd0b9ac4. I think 12 nibbles of the hash is recommended now due to collisions, as is quoting the subject line, e.g. commit bd0b9ac405e1 ("genirq: Remove irq argument from irq flow handlers"). > > Issue detected using Coccinelle (http://coccinelle.lip6.fr/) > > Signed-off-by: Julia Lawall Acked-by: James Hogan Thanks James > > --- > drivers/irqchip/irq-metag-ext.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/irqchip/irq-metag-ext.c b/drivers/irqchip/irq-metag-ext.c > index 8c38b3d..0cdd923 100644 > --- a/drivers/irqchip/irq-metag-ext.c > +++ b/drivers/irqchip/irq-metag-ext.c > @@ -436,7 +436,6 @@ static int meta_intc_irq_set_type(struct irq_data *data, unsigned int flow_type) > > /** > * meta_intc_irq_demux() - external irq de-multiplexer > - * @irq: the virtual interrupt number > * @desc: the interrupt description structure for this irq > * > * The cpu receives an interrupt on TR2 when a SoC interrupt has occurred. It is >