Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755737AbcJFKH1 (ORCPT ); Thu, 6 Oct 2016 06:07:27 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:60997 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755171AbcJFKEO (ORCPT ); Thu, 6 Oct 2016 06:04:14 -0400 Subject: Re: [PATCH 2/9] mtd: spi-nor: add an alternative method to support memory >16MiB To: Cyrille Pitchen , "computersforpeace@gmail.com" , "linux-mtd@lists.infradead.org" References: <75db6c008249df8d0646ea5006648e57fea40706.1475597385.git.cyrille.pitchen@atmel.com> CC: "marex@denx.de" , "boris.brezillon@free-electrons.com" , "nicolas.ferre@atmel.com" , "linux-kernel@vger.kernel.org" From: Vignesh R Message-ID: Date: Thu, 6 Oct 2016 15:33:39 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2049 Lines: 55 On Wednesday 05 October 2016 06:23 PM, Cyrille Pitchen wrote: > Hi Vignesh, > > Le 05/10/2016 ? 14:12, Vignesh R a ?crit : >> Hi, >> >> >> On Tuesday 04 October 2016 10:07 PM, Cyrille Pitchen wrote: >> [...] >>> static struct seq_rw_config stfsm_s25fl_write4_configs[] = { >>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >>> index 5c87b2d99507..423448c1c7a8 100644 >>> --- a/drivers/mtd/spi-nor/spi-nor.c >>> +++ b/drivers/mtd/spi-nor/spi-nor.c >>> @@ -75,6 +75,10 @@ struct flash_info { >>> * bit. Must be used with >>> * SPI_NOR_HAS_LOCK. >>> */ >>> +#define SPI_NOR_4B_OPCODES BIT(10) /* >>> + * Use dedicated 4byte address op codes >>> + * to support memory size above 128Mib. >>> + */ >> >> >> I don't see this flag being added to any flash_info data for any m25p80 >> compatible flashes? Is that part of a separate series? >> > > Indeed, this flag is not used yet by any entry in the spi_nor_ids[] array. > At first, I tested this patch with a Macronix mx25l25673g memory. > This memory shares the very same JEDEC ID as the older mx25l25635e, so > I added the SPI_NOR_4B_OPCODES flag in the mx25l25635e entry during my test. > However I didn't commit this change since the actual mx25l25635e memory > doesn't support The 4-byte address instruction test. > > Also the mx25l25673g provides the optional 4-byte Address Instruction Table, > as described in the JESD216 rev B specification, so patches 6 and 7 allow > to use the 4-byte address op codes without setting the SPI_NOR_4B_OPCODES flag. > > Hence the SPI_NOR_4B_OPCODES, will be useful for memories which don't > provide the JESD216B 4-byte Address Instruction Table but still support > the associated op code. It will have to be tested for each individual entry > in the spi_nor_ids[] array, which can be done later. > > Anyway, the 4-byte address op codes introduced by this patch are also used > by patch 7 (parse SFDP 4-byte Address Instruction Table). OK, thanks for the explanation! -- Regards Vignesh