Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935093AbcJFUeo (ORCPT ); Thu, 6 Oct 2016 16:34:44 -0400 Received: from mail-pa0-f68.google.com ([209.85.220.68]:34558 "EHLO mail-pa0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933715AbcJFUeb (ORCPT ); Thu, 6 Oct 2016 16:34:31 -0400 From: Joshua Clayton To: Alan Tull , Moritz Fischer Cc: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Fabio Estevam , Russell King , Joshua Clayton , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] ARM: dts: imx6q-evi: support cyclonespi Date: Thu, 6 Oct 2016 13:34:19 -0700 Message-Id: <16ba10d2523a6f0eaf40246dfbd9e660f297fd22.1475783742.git.stillcompiling@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <4b4432c04b4ea92a2af814e3d7866c33f2eb12ea.1475783742.git.stillcompiling@gmail.com> References: <4b4432c04b4ea92a2af814e3d7866c33f2eb12ea.1475783742.git.stillcompiling@gmail.com> In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1074 Lines: 43 Add support for Altera cyclone V FPGA connected to an spi port Signed-off-by: Joshua Clayton --- arch/arm/boot/dts/imx6q-evi.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index 6de21ff..7e5d3cf 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -95,6 +95,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>; status = "okay"; + + fpga_spi: cyclonespi@0 { + compatible = "altr,cyclonespi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + pinctrl-0 = <&pinctrl_fpgaspi>; + reset-gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status-gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + }; }; &ecspi3 { @@ -325,6 +334,13 @@ >; }; + pinctrl_fpgaspi: fpgaspigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + pinctrl_gpminand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -- 2.7.4