Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965165AbcJGQnm (ORCPT ); Fri, 7 Oct 2016 12:43:42 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:36937 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965056AbcJGQnI (ORCPT ); Fri, 7 Oct 2016 12:43:08 -0400 From: ahaslam@baylibre.com To: gregkh@linuxfoundation.org, robh+dt@kernel.org, nsekhar@ti.com, stern@rowland.harvard.edu, khilman@baylibre.com, sshtylyov@ru.mvista.com, david@lechnology.com Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Axel Haslam Subject: [PATCH/RFT 01/12] ARM: davinci: da8xx: Enable the usb20 "per" clk on phy_clk_enable Date: Fri, 7 Oct 2016 18:42:46 +0200 Message-Id: <1475858577-10366-2-git-send-email-ahaslam@baylibre.com> X-Mailer: git-send-email 2.7.1 In-Reply-To: <1475858577-10366-1-git-send-email-ahaslam@baylibre.com> References: <1475858577-10366-1-git-send-email-ahaslam@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1665 Lines: 56 From: Axel Haslam While probing ochi phy with usb20 phy as a parent clock for usb11_phy, the usb20_phy clock enable would time out. This is because the usb20 module clock needs to enabled while trying to lock the usb20_phy PLL. Call clk enable and get for the usb20 peripheral before trying to enable the phy PLL. Signed-off-by: Axel Haslam --- arch/arm/mach-davinci/usb-da8xx.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c index 9e41a7f..982e105 100644 --- a/arch/arm/mach-davinci/usb-da8xx.c +++ b/arch/arm/mach-davinci/usb-da8xx.c @@ -53,11 +53,19 @@ int __init da8xx_register_usb_refclkin(int rate) static void usb20_phy_clk_enable(struct clk *clk) { + struct clk *usb20_clk; u32 val; u32 timeout = 500000; /* 500 msec */ val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); + usb20_clk = clk_get(NULL, "usb20"); + if (IS_ERR(usb20_clk)) { + pr_err("could not get usb20 clk\n"); + return; + } + + clk_prepare_enable(usb20_clk); /* * Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 * host may use the PLL clock without USB 2.0 OTG being used. @@ -70,11 +78,14 @@ static void usb20_phy_clk_enable(struct clk *clk) while (--timeout) { val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG)); if (val & CFGCHIP2_PHYCLKGD) - return; + goto done; udelay(1); } pr_err("Timeout waiting for USB 2.0 PHY clock good.\n"); +done: + clk_disable_unprepare(usb20_clk); + clk_put(usb20_clk); } static void usb20_phy_clk_disable(struct clk *clk) -- 2.7.1