Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1758099AbcJHRaE (ORCPT <rfc822;w@1wt.eu>);
        Sat, 8 Oct 2016 13:30:04 -0400
Received: from mga03.intel.com ([134.134.136.65]:7600 "EHLO mga03.intel.com"
        rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP
        id S1757122AbcJHR36 (ORCPT <rfc822;linux-kernel@vger.kernel.org>);
        Sat, 8 Oct 2016 13:29:58 -0400
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.31,462,1473145200"; 
   d="scan'208";a="1042113666"
Date: Sat, 8 Oct 2016 13:33:06 -0700
From: Fenghua Yu <fenghua.yu@intel.com>
To: Nilay Vaish <nilayvaish@gmail.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        "H. Peter Anvin" <h.peter.anvin@intel.com>,
        Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Stephane Eranian <eranian@google.com>, Borislav Petkov <bp@suse.de>,
        Dave Hansen <dave.hansen@intel.com>, Shaohua Li <shli@fb.com>,
        David Carrillo-Cisneros <davidcc@google.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        Sai Prakhya <sai.praneeth.prakhya@intel.com>,
        Vikas Shivappa <vikas.shivappa@linux.intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v3 05/18] Documentation, x86: Documentation for Intel
 resource allocation user interface
Message-ID: <20161008203306.GA7672@linux.intel.com>
References: <1475894763-64683-1-git-send-email-fenghua.yu@intel.com>
 <1475894763-64683-6-git-send-email-fenghua.yu@intel.com>
 <CACbG30_cKCS7Tz2GSosybPycEgGP444U8ebU8_A_AVr84JDs7g@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <CACbG30_cKCS7Tz2GSosybPycEgGP444U8ebU8_A_AVr84JDs7g@mail.gmail.com>
User-Agent: Mutt/1.5.21 (2010-09-15)
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
Content-Length: 1023
Lines: 28

On Sat, Oct 08, 2016 at 12:12:07PM -0500, Nilay Vaish wrote:
> On 7 October 2016 at 21:45, Fenghua Yu <fenghua.yu@intel.com> wrote:
> > From: Fenghua Yu <fenghua.yu@intel.com>
> >
> > +L3 details (code and data prioritization disabled)
> > +--------------------------------------------------
> > +With CDP disabled the L3 schemata format is:
> > +
> > +       L3:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
> > +
> > +L3 details (CDP enabled via mount option to resctrl)
> > +----------------------------------------------------
> > +When CDP is enabled, you need to specify separate cache bit masks for
> > +code and data access. The generic format is:
> > +
> > +       L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
> 
> Can we drop L3 here and instead say:
> L<level>:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
> 
> and similarly for without CDP as well.

L3 and L2 are similar but different. L2 doesn't have CDP feature. It would
be better to talk them separately here.

Thanks.

-Fenghua