Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752008AbcJJU4e (ORCPT ); Mon, 10 Oct 2016 16:56:34 -0400 Received: from alln-iport-1.cisco.com ([173.37.142.88]:23939 "EHLO alln-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751008AbcJJU4d (ORCPT ); Mon, 10 Oct 2016 16:56:33 -0400 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: =?us-ascii?q?A0BzAwBA//tX/5hdJa1dGgEBAQECAQEBA?= =?us-ascii?q?QgBAQEBgzwBAQEBAR2BU32MNqklgg+CC4YggXM4FAECAQEBAQEBAV4nhQ9SKYE?= =?us-ascii?q?VE4hQwRYBAQEBAQUCASURhiyOewWPMopNj3ILgW6OBAKHD4lnHjZLhHoeNIgPA?= =?us-ascii?q?QEB?= X-IronPort-AV: E=Sophos;i="5.31,474,1473120000"; d="scan'208";a="334127461" From: David Singleton To: Andrew Morton Cc: xe-kernel@external.cisco.com, scottwood@freescale.com, linux-kernel@vger.kernel.org Subject: [PATCH] fsl-ifc: set extended addressing for systems whose bootloader doesn't Date: Mon, 10 Oct 2016 13:56:31 -0700 Message-Id: <20161010205631.18404-1-davsingl@cisco.com> X-Mailer: git-send-email 2.9.3 X-Auto-Response-Suppress: DR, OOF, AutoReply Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2381 Lines: 71 For 32bit systems whose bootloader doesn't set the extended 36-bit addressing register for flash devices above the 4GB boundary we can set up in the driver. This patch checks the number of address-cells in the dts file for the fsl-ifc flash controller. If #address-cells is 2 then it's a 36-bit address mapping, so set the extended address register in the ccsr for the upper 0xf address, as specified in the dts file. The code only sets the extended addressing register if the dts defines 36-bit addressing for the flash devices AND the register was not set by the boot loader. If the bootloader has set the extended addressing register the code does not update the register. Cc: xe-kernel@external.cisco.com Cc: scottwood@freescale.com Signed-off-by: David Singleton --- drivers/memory/fsl_ifc.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c index 1b182b1..3d7a52e 100644 --- a/drivers/memory/fsl_ifc.c +++ b/drivers/memory/fsl_ifc.c @@ -78,6 +78,41 @@ EXPORT_SYMBOL(fsl_ifc_find); static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl) { struct fsl_ifc_global __iomem *ifc = ctrl->gregs; + struct device_node *np; + + /* + * enable extended 36-bit addressing + * 24.3.2 Extended Chip Select Property registers (IFC_CSPRn_EXT) + * The extended chip select property register (CSPRn_EXT) contains + * the extended base address, that is, the most significant + * bits (msb) of the base address. + * Set it here for systems where the bootloader doesn't. + */ + np = of_find_compatible_node(NULL, NULL, "fsl,ifc"); + if (np) { + const u32 *prop; + + prop = of_get_property(np, "#address-cells", NULL); + if (prop) { + u32 cells; + /* + * #address-cells 2 means 36-bit addresses are used + * and the if cspr_ext register is zero, the + * bootloader didn't set it, we'll set it manually + */ + cells = of_n_addr_cells(np); + if ((cells == 2) && !(ifc_in32(&ifc->cspr_cs[0].cspr_ext))) { + prop = of_get_property(np, "reg", NULL); + if (prop) { + u32 extaddr; + + extaddr = *prop; /* get the top nibble for 36-bit */ + pr_info("fsl-ifc extended 36-bit addressing\n"); + ifc_out32(extaddr, &ifc->cspr_cs[0].cspr_ext); + } + } + } + } /* * Clear all the common status and event registers -- 2.9.3