Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752103AbcJKTgU (ORCPT ); Tue, 11 Oct 2016 15:36:20 -0400 Received: from mga03.intel.com ([134.134.136.65]:27371 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750717AbcJKTgS (ORCPT ); Tue, 11 Oct 2016 15:36:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,330,1473145200"; d="scan'208";a="178841827" Message-ID: <1476214572.2460.14.camel@intel.com> Subject: Re: [Intel-gfx] [PATCH v2 01/10] drm/i915/skl: Move per-pipe ddb allocations into crtc states From: Paulo Zanoni To: Lyude , intel-gfx@lists.freedesktop.org Cc: David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Daniel Vetter Date: Tue, 11 Oct 2016 16:36:12 -0300 In-Reply-To: <1475885497-6094-2-git-send-email-cpaul@redhat.com> References: <1475885497-6094-1-git-send-email-cpaul@redhat.com> <1475885497-6094-2-git-send-email-cpaul@redhat.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.20.5 (3.20.5-1.fc24) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 8798 Lines: 259 Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > First part of cleaning up all of the skl watermark code. This moves > the > structures for storing the ddb allocations of each pipe into > intel_crtc_state, along with moving the structures for storing the > current ddb allocations active on hardware into intel_crtc. > > Changes since v1: > - Don't replace alloc->start = alloc->end = 0; > > Signed-off-by: Lyude Reviewed-by: Paulo Zanoni > Reviewed-by: Maarten Lankhorst > Cc: Ville Syrjälä > Cc: Paulo Zanoni > --- >  drivers/gpu/drm/i915/i915_drv.h      |  1 - >  drivers/gpu/drm/i915/intel_display.c | 16 ++++++++------- >  drivers/gpu/drm/i915/intel_drv.h     |  8 +++++--- >  drivers/gpu/drm/i915/intel_pm.c      | 40 +++++++++++++++----------- > ---------- >  4 files changed, 30 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h > index a219a35..bb2de8d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1637,7 +1637,6 @@ static inline bool skl_ddb_entry_equal(const > struct skl_ddb_entry *e1, >  } >   >  struct skl_ddb_allocation { > - struct skl_ddb_entry pipe[I915_MAX_PIPES]; >   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; > /* packed/uv */ >   struct skl_ddb_entry > y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; >  }; > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index a366656..17733af 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -14235,12 +14235,11 @@ static void skl_update_crtcs(struct > drm_atomic_state *state, >        unsigned int *crtc_vblank_mask) >  { >   struct drm_device *dev = state->dev; > - struct drm_i915_private *dev_priv = to_i915(dev); >   struct intel_atomic_state *intel_state = > to_intel_atomic_state(state); >   struct drm_crtc *crtc; > + struct intel_crtc *intel_crtc; >   struct drm_crtc_state *old_crtc_state; > - struct skl_ddb_allocation *new_ddb = &intel_state- > >wm_results.ddb; > - struct skl_ddb_allocation *cur_ddb = &dev_priv- > >wm.skl_hw.ddb; > + struct intel_crtc_state *cstate; >   unsigned int updated = 0; >   bool progress; >   enum pipe pipe; > @@ -14258,12 +14257,14 @@ static void skl_update_crtcs(struct > drm_atomic_state *state, >   for_each_crtc_in_state(state, crtc, old_crtc_state, > i) { >   bool vbl_wait = false; >   unsigned int cmask = drm_crtc_mask(crtc); > - pipe = to_intel_crtc(crtc)->pipe; > + > + intel_crtc = to_intel_crtc(crtc); > + cstate = to_intel_crtc_state(crtc->state); > + pipe = intel_crtc->pipe; >   >   if (updated & cmask || !crtc->state->active) >   continue; > - if (skl_ddb_allocation_overlaps(state, > cur_ddb, new_ddb, > - pipe)) > + if (skl_ddb_allocation_overlaps(state, > intel_crtc)) >   continue; >   >   updated |= cmask; > @@ -14274,7 +14275,8 @@ static void skl_update_crtcs(struct > drm_atomic_state *state, >    * then we need to wait for a vblank to pass > for the >    * new ddb allocation to take effect. >    */ > - if (!skl_ddb_allocation_equals(cur_ddb, > new_ddb, pipe) && > + if (!skl_ddb_entry_equal(&cstate- > >wm.skl.ddb, > +  &intel_crtc- > >hw_ddb) && >       !crtc->state->active_changed && >       intel_state->wm_results.dirty_pipes != > updated) >   vbl_wait = true; > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index f48e79a..35ba282 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -496,6 +496,7 @@ struct intel_crtc_wm_state { >   struct { >   /* gen9+ only needs 1-step wm programming */ >   struct skl_pipe_wm optimal; > + struct skl_ddb_entry ddb; >   >   /* cached plane data rate */ >   unsigned plane_data_rate[I915_MAX_PLANES]; > @@ -733,6 +734,9 @@ struct intel_crtc { >   bool cxsr_allowed; >   } wm; >   > + /* gen9+: ddb allocation currently being used */ > + struct skl_ddb_entry hw_ddb; > + >   int scanline_offset; >   >   struct { > @@ -1755,9 +1759,7 @@ bool skl_ddb_allocation_equals(const struct > skl_ddb_allocation *old, >          const struct skl_ddb_allocation *new, >          enum pipe pipe); >  bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state, > -  const struct skl_ddb_allocation > *old, > -  const struct skl_ddb_allocation > *new, > -  enum pipe pipe); > +  struct intel_crtc *intel_crtc); >  void skl_write_cursor_wm(struct intel_crtc *intel_crtc, >    const struct skl_wm_values *wm); >  void skl_write_plane_wm(struct intel_crtc *intel_crtc, > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index fe6c1c6..68355b0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3058,7 +3058,6 @@ skl_ddb_get_pipe_allocation_limits(struct > drm_device *dev, >   struct drm_crtc *for_crtc = cstate->base.crtc; >   unsigned int pipe_size, ddb_size; >   int nth_active_pipe; > - int pipe = to_intel_crtc(for_crtc)->pipe; >   >   if (WARN_ON(!state) || !cstate->base.active) { >   alloc->start = 0; > @@ -3086,7 +3085,7 @@ skl_ddb_get_pipe_allocation_limits(struct > drm_device *dev, >    * we currently hold. >    */ >   if (!intel_state->active_pipe_changes) { > - *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe]; > + *alloc = to_intel_crtc(for_crtc)->hw_ddb; >   return; >   } >   > @@ -3354,7 +3353,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state > *cstate, >   struct drm_plane *plane; >   struct drm_plane_state *pstate; >   enum pipe pipe = intel_crtc->pipe; > - struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; > + struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb; >   uint16_t alloc_size, start, cursor_blocks; >   uint16_t *minimum = cstate->wm.skl.minimum_blocks; >   uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks; > @@ -3370,7 +3369,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state > *cstate, >   return 0; >   >   if (!cstate->base.active) { > - ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0; > + alloc->start = alloc->end = 0; >   return 0; >   } >   > @@ -3897,14 +3896,6 @@ void skl_write_cursor_wm(struct intel_crtc > *intel_crtc, >       &wm->ddb.plane[pipe][PLANE_CURSOR]); >  } >   > -bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old, > -        const struct skl_ddb_allocation *new, > -        enum pipe pipe) > -{ > - return new->pipe[pipe].start == old->pipe[pipe].start && > -        new->pipe[pipe].end == old->pipe[pipe].end; > -} > - >  static inline bool skl_ddb_entries_overlap(const struct > skl_ddb_entry *a, >      const struct > skl_ddb_entry *b) >  { > @@ -3912,22 +3903,22 @@ static inline bool > skl_ddb_entries_overlap(const struct skl_ddb_entry *a, >  } >   >  bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state, > -  const struct skl_ddb_allocation > *old, > -  const struct skl_ddb_allocation > *new, > -  enum pipe pipe) > +  struct intel_crtc *intel_crtc) >  { > - struct drm_device *dev = state->dev; > - struct intel_crtc *intel_crtc; > - enum pipe otherp; > + struct drm_crtc *other_crtc; > + struct drm_crtc_state *other_cstate; > + struct intel_crtc *other_intel_crtc; > + const struct skl_ddb_entry *ddb = > + &to_intel_crtc_state(intel_crtc->base.state)- > >wm.skl.ddb; > + int i; >   > - for_each_intel_crtc(dev, intel_crtc) { > - otherp = intel_crtc->pipe; > + for_each_crtc_in_state(state, other_crtc, other_cstate, i) { > + other_intel_crtc = to_intel_crtc(other_crtc); >   > - if (otherp == pipe) > + if (other_intel_crtc == intel_crtc) >   continue; >   > - if (skl_ddb_entries_overlap(&new->pipe[pipe], > -     &old->pipe[otherp])) > + if (skl_ddb_entries_overlap(ddb, &other_intel_crtc- > >hw_ddb)) >   return true; >   } >   > @@ -4092,7 +4083,6 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst, >   memcpy(dst->plane_trans[pipe], src->plane_trans[pipe], >          sizeof(dst->plane_trans[pipe])); >   > - dst->ddb.pipe[pipe] = src->ddb.pipe[pipe]; >   memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe], >          sizeof(dst->ddb.y_plane[pipe])); >   memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], > @@ -4200,6 +4190,8 @@ static void skl_update_wm(struct drm_crtc > *crtc) >   >   skl_copy_wm_for_pipe(hw_vals, results, pipe); >   > + intel_crtc->hw_ddb = cstate->wm.skl.ddb; > + >   mutex_unlock(&dev_priv->wm.wm_mutex); >  } >