Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751547AbcJLEOd (ORCPT ); Wed, 12 Oct 2016 00:14:33 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:49341 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750721AbcJLEOc (ORCPT ); Wed, 12 Oct 2016 00:14:32 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED4: 1 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: nsekhar@ti.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <7e1c5a23f5b216e016380b0908a62848> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 3/4] PCI: dra7xx: Add support to force RC to work in GEN1 mode To: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring References: <1476190715-16884-1-git-send-email-kishon@ti.com> <1476190715-16884-4-git-send-email-kishon@ti.com> Cc: shawn.lin@rock-chips.com, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, nsekhar@ti.com From: Shawn Lin Message-ID: Date: Wed, 12 Oct 2016 12:14:20 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1476190715-16884-4-git-send-email-kishon@ti.com> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3762 Lines: 111 On 2016/10/11 20:58, Kishon Vijay Abraham I wrote: > PCIe in AM57x/DRA7x devices is by default > configured to work in GEN2 mode. However there > may be situations when working in GEN1 mode is > desired. One example is limitation i925 (PCIe GEN2 > mode not supported at junction temperatures < 0C). > Just a drive-by comment. Seems there are already much more requirments for host drivers to know the limitation of link speed, so I pushed patches recently to consolidate it for host drivers[0] suggested by Rob. So maybe you could use that instead. :) [0] https://patchwork.kernel.org/patch/9371931/ https://patchwork.kernel.org/patch/9371929/ > Add support to force Root Complex to work in GEN1 > mode if so desired, but don't force GEN1 mode on > any board just yet. > > Signed-off-by: Kishon Vijay Abraham I > Signed-off-by: Sekhar Nori > --- > Documentation/devicetree/bindings/pci/ti-pci.txt | 1 + > drivers/pci/host/pci-dra7xx.c | 27 ++++++++++++++++++++++ > 2 files changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt > index 60e2516..a3d6ca3 100644 > --- a/Documentation/devicetree/bindings/pci/ti-pci.txt > +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt > @@ -25,6 +25,7 @@ PCIe Designware Controller > > Optional Property: > - gpios : Should be added if a gpio line is required to drive PERST# line > + - ti,pcie-is-gen1 : Force the PCIe controller to work in GEN1 (2.5 GT/s). > > Example: > axi { > diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c > index 4ccba6d..2a669cb 100644 > --- a/drivers/pci/host/pci-dra7xx.c > +++ b/drivers/pci/host/pci-dra7xx.c > @@ -63,11 +63,14 @@ > #define LINK_UP BIT(16) > #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF > > +#define EXP_CAP_ID_OFFSET 0x70 > + > struct dra7xx_pcie { > struct pcie_port pp; > void __iomem *base; /* DT ti_conf */ > int phy_count; /* DT phy-names count */ > struct phy **phy; > + bool is_gen1; > }; > > #define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp) > @@ -96,12 +99,33 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx_pcie) > struct pcie_port *pp = &dra7xx_pcie->pp; > struct device *dev = pp->dev; > u32 reg; > + u32 exp_cap_off = EXP_CAP_ID_OFFSET; > > if (dw_pcie_link_up(pp)) { > dev_err(dev, "link is already up\n"); > return 0; > } > > + if (dra7xx_pcie->is_gen1) { > + dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > + 4, ®); > + if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > + reg &= ~((u32)PCI_EXP_LNKCAP_SLS); > + reg |= PCI_EXP_LNKCAP_SLS_2_5GB; > + dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCAP, 4, reg); > + } > + > + dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > + 2, ®); > + if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > + reg &= ~((u32)PCI_EXP_LNKCAP_SLS); > + reg |= PCI_EXP_LNKCAP_SLS_2_5GB; > + dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCTL2, 2, reg); > + } > + } > + > reg = dra7xx_pcie_readl(dra7xx_pcie, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); > reg |= LTSSM_EN; > dra7xx_pcie_writel(dra7xx_pcie, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); > @@ -402,6 +426,9 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) > reg &= ~LTSSM_EN; > dra7xx_pcie_writel(dra7xx_pcie, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); > > + if (of_property_read_bool(np, "ti,pcie-is-gen1")) > + dra7xx_pcie->is_gen1 = true; > + > ret = dra7xx_add_pcie_port(dra7xx_pcie, pdev); > if (ret < 0) > goto err_gpio; > -- Best Regards Shawn Lin