Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755862AbcJMMqe (ORCPT ); Thu, 13 Oct 2016 08:46:34 -0400 Received: from 1.mo5.mail-out.ovh.net ([188.165.57.91]:34371 "EHLO 1.mo5.mail-out.ovh.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754985AbcJMMq1 (ORCPT ); Thu, 13 Oct 2016 08:46:27 -0400 X-Greylist: delayed 601 seconds by postgrey-1.27 at vger.kernel.org; Thu, 13 Oct 2016 08:46:26 EDT MIME-Version: 1.0 In-Reply-To: <20161013110317.ee6by6njrvs53ztx@piout.net> References: <20161007163427.11454-1-alexandre.belloni@free-electrons.com> <20161007163427.11454-3-alexandre.belloni@free-electrons.com> <20161013110317.ee6by6njrvs53ztx@piout.net> From: Jean-Jacques Hiblot Date: Thu, 13 Oct 2016 14:27:15 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/2] power/reset: at91-poweroff: timely shitdown LPDDR memories To: Alexandre Belloni Cc: Jean-Jacques Hiblot , Sebastian Reichel , Dmitry Eremin-Solenikov , Nicolas Ferre , Linux Kernel Mailing List , "linux-arm-kernel@lists.infradead.org" , linux-pm@vger.kernel.org Content-Type: text/plain; charset=UTF-8 X-Ovh-Tracer-Id: 9065183102216853527 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelvddrgeeggdehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2311 Lines: 63 2016-10-13 13:03 GMT+02:00 Alexandre Belloni : > On 12/10/2016 at 14:48:27 +0200, Jean-Jacques Hiblot wrote : >> > +static void at91_lpddr_poweroff(void) >> > +{ >> > + asm volatile( >> > + /* Align to cache lines */ >> > + ".balign 32\n\t" >> > + >> > + " ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t" >> At first sight, it looks useless. I assume it's used to preload the >> TLB before the LPDDR is turned off. >> A comment to explain why this line is useful would prevent its removal. > > Yes, this is the case. I can add a comment. > > Anyway, I would prefer the whole thing to run from SRAM, as a PIE > instead of relying on the cache. Instead of copying into the SRAM, you can make the cache reliable by preloading it, much like the TLB. LDI is probably not available for most of atmel's SOC, so the only way I can think of, is to execute code from the targeted area. here is an example: + /* + * Jump to the end of the sequence to preload instruction cache + * It only works because the sequence is short enough not to + * sit accross more than 2 cache lines + */ + " b end_of_sequence\n\t" + "start_of_sequence:\n\t" + /* Power down SDRAM0 */ " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t" /* Shutdown CPU */ " str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t" " b .\n\t" + + /* + * we're now 100% sure that the code to shutdown the LPDDR and + * the CPU is in cache, go back to do the actual job + */ + "end_of_sequence:\n\t" + " b start_of_sequence\n\t" : > >> > + ddr_type = readl(mpddrc_base + AT91_DDRSDRC_MDR) & AT91_DDRSDRC_MD; >> > + if ((ddr_type == AT91_DDRSDRC_MD_LPDDR2) || >> > + (ddr_type == AT91_DDRSDRC_MD_LPDDR3)) >> Souldn't there be something like "pm_power_off = at91_lpddr_poweroff;" here ? >> > > Indeed > > > -- > Alexandre Belloni, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com