Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756448AbcJPOOY (ORCPT ); Sun, 16 Oct 2016 10:14:24 -0400 Received: from mail.skyhub.de ([78.46.96.112]:44605 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753709AbcJPOOP (ORCPT ); Sun, 16 Oct 2016 10:14:15 -0400 Date: Sun, 16 Oct 2016 16:22:33 +0200 From: Borislav Petkov To: Ingo Molnar , peterz@infradead.org, tglx@linutronix.de, dave.hansen@intel.com, torvalds@linux-foundation.org, piotr.luc@intel.com, luto@kernel.org, brgerst@gmail.com, hpa@zytor.com, linux-kernel@vger.kernel.org, dvlasenk@redhat.com, jpoimboe@redhat.com Cc: linux-tip-commits@vger.kernel.org Subject: Re: [tip:x86/urgent] x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features Message-ID: <20161016142233.xuqrahty6gcwq7en@pd.tnic> References: <20161012175731.29619-1-piotr.luc@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/ (1.7.0) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3020 Lines: 74 On Sun, Oct 16, 2016 at 04:21:49AM -0700, tip-bot for Piotr Luc wrote: > Commit-ID: a518dcc82b6162009c8ca3d169fe61c81536ff17 > Gitweb: http://git.kernel.org/tip/a518dcc82b6162009c8ca3d169fe61c81536ff17 > Author: Piotr Luc > AuthorDate: Wed, 12 Oct 2016 19:57:31 +0200 > Committer: Ingo Molnar > CommitDate: Sun, 16 Oct 2016 11:32:11 +0200 > > x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features > > AVX512_4VNNIW - Vector instructions for deep learning enhanced word > variable precision. > AVX512_4FMAPS - Vector instructions for deep learning floating-point > single precision. > > The new instructions are to be used in future Intel Xeon & Xeon Phi > processors. > > The spec can be found in Intel Software Developer Manual or in > Instruction Set Extensions Programming Reference. See > https://software.intel.com/sites/default/files/managed/69/78/319433-025.pdf. > > Signed-off-by: Piotr Luc > Reviewed-by: Dave Hansen > Cc: Andy Lutomirski > Cc: Borislav Petkov > Cc: Brian Gerst > Cc: Denys Vlasenko > Cc: H. Peter Anvin > Cc: Josh Poimboeuf > Cc: Linus Torvalds > Cc: Peter Zijlstra > Cc: Thomas Gleixner > Link: http://lkml.kernel.org/r/20161012175731.29619-1-piotr.luc@intel.com > Signed-off-by: Ingo Molnar ... > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 1188bc8..6697b75 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -12,7 +12,7 @@ > /* > * Defines x86 CPU feature bits > */ > -#define NCAPINTS 18 /* N 32-bit words worth of info */ > +#define NCAPINTS 19 /* N 32-bit words worth of info */ > #define NBUGINTS 1 /* N 32-bit bug flags */ > > /* > @@ -285,6 +285,10 @@ > #define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */ > #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ > > +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx), word 18 */ > +#define X86_FEATURE_AVX512_4VNNIW (18*32+2) /* AVX-512 Neural Network Instructions */ > +#define X86_FEATURE_AVX512_4FMAPS (18*32+3) /* AVX-512 Multiply Accumulation Single precision */ This is getting ridiculous: we keep adding new leafs to ->x86_capability, thus bloating cpuinfo_x86 but then it is not even worth it - this patch defines only two bits. I know, I know, it is a CPUID leaf of features, we will need them, yadda yadda but until we do, I'd suggest these all new feature bits to to init_scattered_cpuid_features() and be carved out to a leaf of their own *only* when we really, actually add them and fill up that leaf. Otherwise, we have one fat and sparse x86_capability array. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.