Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932813AbcJQIr6 (ORCPT ); Mon, 17 Oct 2016 04:47:58 -0400 Received: from mail-lf0-f68.google.com ([209.85.215.68]:36017 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757712AbcJQIrt (ORCPT ); Mon, 17 Oct 2016 04:47:49 -0400 Date: Mon, 17 Oct 2016 10:47:43 +0200 From: Ingo Molnar To: "Luc, Piotr" Cc: "tglx@linutronix.de" , "bp@alien8.de" , "peterz@infradead.org" , "linux-kernel@vger.kernel.org" , "torvalds@linux-foundation.org" , "linux-tip-commits@vger.kernel.org" , "jpoimboe@redhat.com" , "hpa@zytor.com" , "brgerst@gmail.com" , "luto@kernel.org" , "Hansen, Dave" , "dvlasenk@redhat.com" Subject: Re: [tip:x86/urgent] x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS features Message-ID: <20161017084743.GB9462@gmail.com> References: <20161012175731.29619-1-piotr.luc@intel.com> <20161016142233.xuqrahty6gcwq7en@pd.tnic> <1476692185.27884.7.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1476692185.27884.7.camel@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1969 Lines: 58 * Luc, Piotr wrote: > On Mon, 2016-10-17 at 09:55 +0200, Thomas Gleixner wrote: > > On Sun, 16 Oct 2016, Borislav Petkov wrote: > > > > > > > > > > > The spec can be found in Intel Software Developer Manual or in > > > > Instruction Set Extensions Programming Reference. See > > > > https://software.intel.com/sites/default/files/managed/69/78/3194 > > > > 33-025.pdf. > > > > > > > > > > > +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx), > > > > word 18 */ > > > > +#define X86_FEATURE_AVX512_4VNNIW??(18*32+2) /* AVX-512 Neural > > > > Network Instructions */ > > > > +#define X86_FEATURE_AVX512_4FMAPS??(18*32+3) /* AVX-512 Multiply > > > > Accumulation Single precision */ > > > > > > This is getting ridiculous: we keep adding new leafs to > > > ->x86_capability, thus bloating cpuinfo_x86 but then it is not even > > > worth it - this patch defines only two bits. > > > > What's worse is that the Instruction Set Extensions Programming > > Reference > > manual says: > > > > CPUID.(EAX=07H, ECX=0):EDX[bit 02] AVX512_4FMAPS > > CPUID.(EAX=07H, ECX=0):EBX[bit 03] AVX512_4VNNIW > > > > So AVX512_4VNNIW is in EBX not EDX. What's correct here? The manual > > or the patch? > > > > I'm going to zap it. > > > The manual contains the typo in ?table 2.1 on page 2.2. > Please compare it to the detailed description of CPUID in table 4.8 on > page 2-16. > There manual groups both new bits under EDX: > > EDX ? ?Bits 01 - 00: Reserved > ? ? ? ?Bit 02: AVX512_4VNNIW (Vector instructions for deep learning > enhanced word variable precision.) > ? ? ? ?Bit 03: AVX512_4FMAPS (Vector instructions for deep learning > floating-point single precision.) > ? ? ? ?Bits 31-04: Reserved > > The typo was acknowledged and is going to be fixed in next version of > the document.? All of this should be pointed out in the changelog. I've zapped the commit for the time being - let's iterate this once more, ok? Thanks, Ingo