Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935642AbcJQQZd (ORCPT ); Mon, 17 Oct 2016 12:25:33 -0400 Received: from mail-sn1nam02on0088.outbound.protection.outlook.com ([104.47.36.88]:25440 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965044AbcJQQZM (ORCPT ); Mon, 17 Oct 2016 12:25:12 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=pass (signature was verified) header.d=altera.onmicrosoft.com;vger.kernel.org; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=atull@opensource.altera.com; From: Alan Tull To: Rob Herring CC: Frank Rowand , Mark Rutland , Greg Kroah-Hartman , Moritz Fischer , Ian Campbell , Jon Masters , Michal Simek , Jonathan Corbet , "Cyril Chemparathy" , Matthew Gerlach , Dinh Nguyen , , , , , , Alan Tull Subject: [PATCH v20 01/10] fpga: add bindings document for fpga region Date: Mon, 17 Oct 2016 11:09:32 -0500 Message-ID: <20161017160941.4205-2-atull@opensource.altera.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161017160941.4205-1-atull@opensource.altera.com> References: <20161017160941.4205-1-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BLUPR16CA0005.namprd16.prod.outlook.com (10.164.14.15) To BN3PR03MB1512.namprd03.prod.outlook.com (10.163.35.150) X-MS-Office365-Filtering-Correlation-Id: 1ed5e432-cb08-417f-d32b-08d3f6a808c5 X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1512;2:Jl2cplTU3j7Hlf9PxnH0epO6uwV+uy71BoUEQrVN+48s1R3VvGkuJzwv7pBGzJFpfTsFVlRMaA4ez4zw/Nccl3LlkrD9qejyWbach/Vgjm7NRa8RIKXLTUeTvMn81BnVCK8+XCnpaSe79LbLF87Hmhb1FCzlHXL1IgbtBKtjuV50BqGR8iU2rlrjMLu+0wP6omqcBZFQyiAMV/w+9jRz6g==;3:ynZs7lo3GBaUJaZ9TMeWxKHeqDdh6hmK23XnZSZ4jnU2f4An9AXUfK0+6crQD+6cICdKl7E1IdYaseooDIU9pO4W8s0w4eRC2LHGRnX4AYmGoO1n5Ff+ccJcunARAVOz+IHiVWeUUYkehLdGoaG69g== X-Microsoft-Antispam-Untrusted: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1512; X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1512;25:mRPNYeuW/XjsOvJclioszyWcMka+2EOO4dGCQ3oqb1WbInNThdd6QIUCytuwkJi5qInVLgLRZ3+uDKjvGjv+INJNs0rxZ15YoQA831wgvnYi1q33+YxHYHOKAXcn1zrRh+5vYWXIIDC5DPcQoxyjvWY6C+eV+S+VOo6dnTPQluL8T9QeqW/Ol/4QFIh+TfvEI2Mes+pN9WPcrqUq5NF/BVz5VV2BPg0Y4PkEWMUSKkez2CL/WY3vNpvpQXcUM9mDfAjsb/nOGpTdzu9/ck4hS2H+DYRDrp9fikbAxSUFxFzMBZ/NvO/53akMDwqOepLqyExv7TbnCplrPoh5+AGHrd6M3R+2ZisR5krGP+Cz9rwKqpn9RgKXgbjCEGS3jDdJbG3FL2DtoG9r6IEtTwFPS1fboMwvXsInidyWPTw8Usn0p04ZVEbjePhJnIjd0gdFf58NdXLRXL8W2Xnb1iyzTAz82lbQJvn8qVHT0pf7loN18d9L6pxuwKyCR73hp3PO+QLlyYFPk8724F1qQDqsO53JpyNJyHyjWHAnQgoBhvosRJnfaf+D75mifxmaoYkJIPBgCQdSphTPjw7sUWK041aHXDn3HnQDBNrsSHhP3YIimr2I1tVfDb+vl0BAN99Yrq68n1UvPh9uyoQRKEMpHjjqR3c+oX/j0JjwOrJWEx7KFIPd6Mzav4BgL3azeUzlOhGo/uGiZqWZAPplgJE/4zbfZxdbYwhzwUPJ+Tf3+ZGin9hLExy1TKwYFH+jbNZ4wOvYrUCFCiH67liSXkymrb7KllVCewbY5ZoMSUgSFYdtGSSoKIpfjXpDc0TDmOJUusO629Tsavt+F9uvFHWhEJmHlhLoJld5hfhFyPySmyoYpVwySJVufrn8ubKkYkZEZAmbEA1L9c43BpSXw6iZXw== X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1512;31:ZKnBXUikCThxhqe4U/+3giNWVQ+rAx1FFdfGjWf5pQGkaBQXflxFwJRxjejpAoXh+AJZ9x+IAHPQdf5skJsIxlBNjp4juSrh/ouj/SHUUkb5pd14sCoyyO1kqNmdICUyXU1uADohnnjf03JW3/qLvwPNokMFViV4RxHU7z3tESeGpdIuclzMK4mVflQtX3MWWFA1GWfr5S0h5PTW1L8e+Q3Z/YxEjpEU58e//kGbGEl/9Z4NofulwrshlOiTsy9byutZzN0zlp08VD7lcfKJZg==;20:U06/+VI90gxjD1A87No0eeHjpOmkHsOEvQ9H9FOpIlr7x+HXcG6bjN2N2OcitJmjbWvRWUpDvGy30jTRchU7oRJqSaO3aCo9CZP/d5FzKAIEKl7rEwJOspaq1cprwq7riAw/JiwkkhWcicqHFt+c1TCaypHKt11aUDGmHIOjGvY= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(34691856369561)(52743740316358)(131327999870524)(80048183373757)(788757137089)(192813158149592)(189271028609987);UriScan:(34691856369561)(52743740316358)(131327999870524)(80048183373757)(788757137089)(192813158149592)(189271028609987); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6055026);SRVR:BN3PR03MB1512;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1512;BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(13024025)(5005006)(13023025)(13018025)(13017025)(8121501046)(13015025)(10201501046)(3002001)(6055026);SRVR:CY4PR03MB2757;BCL:0;PCL:0;RULEID:;SRVR:CY4PR03MB2757; X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1512;4:qxnhVhii3QRWYa3I59bmbXqjRIPVpBlCscN3kIxBL0zHMFxH6Ue3eSYERmuvhDkG02AI1SnvTL9FEEPBrRMmnkQlYLyhunfcHR51C74vVumXS7eaXQjxF2p8rAHSsVi0ViNjERAoCn+u2g9HaLeL4++YfPZlUu2pgzZ1hmcC3qbZ903OPt8U933HBCV5RUaGPk5AkLfVQobtUnLkziMDyKIkdRP/dYV43awauy+omdTP7drp+ahZlqEt64dexHFgJjCNL3jN9pTvnjCnm8B7yrrlj3lWgRrus9QQ8s6PfJJy7Wr0Oh2kL66SAgCpsJs5lB0Z8gjszEJanrtpP/1FNt1fvkY7s300IeQFL/wkprAYsnps/fqP5zrZmHD5lgwZI0e6YrIRrbMGzLhcDrUxRbFOGz18v99kotA0eLzu1TwqvIXsLwt+GkMzFdNKr3wBzfUrYIXcYtpLSNfK95v0FHj8lzT/kSY9Pm1XiUsUH3AHALQCJ1qZwTYhbzpsWbuQImDAm0gCHN3wleITqBj2ygzYWvY4nGRli/F9AmTy7NYaC5yvS3fb7zVxfx2zVH57GxjHDDFIr6Zatr/hbvJC+LnzuUCreVPOPcDDZZoX/GBalgEYBdkVd9oijhLN4i7+UPVN7Shm7IG99kYWOVbPnymH98ZxOgaIEz8Edhb98aY= X-Forefront-PRVS: 0098BA6C6C X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4630300001)(6009001)(7916002)(199003)(189002)(4326007)(8666005)(5660300001)(53416004)(8676002)(48376002)(50466002)(86362001)(15974865002)(110136003)(42186005)(50226002)(7520500002)(50986999)(76176999)(4001430100002)(101416001)(33646002)(6666003)(2950100002)(42882006)(5003940100001)(229853001)(15975445007)(106356001)(77096005)(68736007)(66066001)(97736004)(7846002)(107886002)(7416002)(189998001)(7736002)(47776003)(92566002)(105586002)(586003)(6116002)(19580405001)(19580395003)(2906002)(81166006)(305945005)(1076002)(69596002)(3846002)(81156014)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:BN3PR03MB1512;H:linuxheads99.altera.com;FPR:;SPF:None;PTR:InfoNoRecords;A:0;MX:1;LANG:en; X-Microsoft-Exchange-Diagnostics-untrusted: =?us-ascii?Q?1;BN3PR03MB1512;23:h168wFKd+fR/HheBHAgS6etLcISoueCJM0Xn2WPUM?= =?us-ascii?Q?iCajA5ehOwC/SvixupBHIHC7DnIQ5joNE+m0eijhl1g5Y43nsFRZ0y9sVUjY?= =?us-ascii?Q?Hk7ZqQWflwaqNcYMcNZTCSUVqBX1Tg5uB0LcLRVV/tAkMDlBGh6vVh2r51ok?= =?us-ascii?Q?4x3UdUGw1JWBlVKonKeWGwZ8Sc4cEPIlIsHekRNs9yBGAKleet1UEupwh172?= =?us-ascii?Q?P9qntbMt4bmsgFRWMO49i5TEcYEfELmdf6hAeAbDY8dp4W/HmCIMWRhuL2Z0?= =?us-ascii?Q?yDYygG8Cxpze5CpiA77GRvK5qUIABAAm7D+zcT+LuV8CcbDI4AcrLOHBzVG2?= =?us-ascii?Q?TlfcitiQWRI5Cs7n8aKcaAqwtCA/I76YYrBcS4aaaDY9ihOgSG3UTph8hA+Y?= =?us-ascii?Q?clj51l6esUD8mdThF6YA8b/oA20HISbvyDrFRJJEl8AF/p7I4QkTvppKcSq0?= =?us-ascii?Q?e4Wb+LEwiJ8LSvzH25qGMgloOJEsMDGpb9hOaLeXdWQ1Ma7Plsdu7r4mb/Ea?= =?us-ascii?Q?GtgBkL4GVEsdXjeKPzTjAnZGhwTSYTdJOBdlmUkcs++8yUQykr+dk5xviQhf?= =?us-ascii?Q?QK4n7on3APxfMayTlljJj8GCos9bQ9r454GV+waSEPOLmw8GUu/MYlPPg6zu?= =?us-ascii?Q?3WOAp97hyfue1Ld/vZSPOcspyU1pBosZrfyV2Z0NElJ62ub88DTV7ulGEr0W?= =?us-ascii?Q?41D8n5kkO3ztlZgn8gG0Gol7v6u7Su0lheq3Qn3y9OS5+quoUr9QN5exJl9F?= =?us-ascii?Q?cKOt/lXk3n/IeY2qwF9ZychKHjeWEFPiz/E2gk+R6dwaK/NLOOnRNV86dZrE?= =?us-ascii?Q?RwRRzsLQ4IL/K25tMuqBMrBZ86qZ9zjN016rfWFVQaJA9t5KmE9UHpFaSdu9?= =?us-ascii?Q?a4jmxty/Sbz6RQxTCTUYoL0Fc11M3Tv48dEcLT+Yl0tq9OBjuir1Xb3NYdEI?= =?us-ascii?Q?TKbo08nZ+mdOubhbFNxukVWb0wP0kcEeowKGvFFtxzpj346nG7vM5fcZZZl3?= =?us-ascii?Q?YWTr+ppmUyU/q98BgPKxXOKvtk+Z6xT6ngty/hfu6wQ/h/cm+ZIlOKJqvrrV?= =?us-ascii?Q?Ww073cuXNJEtjCITK4kvZWTXwWZldEv6VuHULItxyHqTk3FXy0qW3JDJuVCA?= =?us-ascii?Q?jVCmVpSjLHfJIh07qZJkV5LWJmu2T4zKTgUMKKQPHpFZpPtWXbdRh9XGQIPd?= =?us-ascii?Q?31cXOukuMYvF5wzuodniX/OvVakTY5OYlApjeZXvhbkzS+UCkJDIeyERGxVN?= =?us-ascii?Q?JGbRpxpKNKhYk4AwlXzoJxB8ZzxXo7Bu6dBoQFuS8Kg1JQVWyQ0kNYHpx8gF?= =?us-ascii?Q?qDKg6JE6OYUEC8s4zGO530=3D?= X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1512;6:zl0ytFn1bTf0f+ahALZ2Lk72uBDd8qN/vqzR4e9pf/wnq+OfUQWeSBMooRAfPMWPqvID+rTVJbgSYAszXcut5QuX7OflWU+Hs+LfjyCTPATyglpDZAX54MVkhJqTxfWa1f5NG1rbXi7kBvGsnt40j4H2eEDEP0ES/6PO6hMDCt6huEx57E9FLIW967M5tY0fxxt9oVayiYKlr2Q+MQc5mU9XpUp84q0D9Fno88P3qDwDOBxL2V8OfZI3JaKbu/px3uzVDHkmfuBpaAW31EjSOHZT5Uo0W8W4NlOiIDHA6rtS09rJ/BRlzWdI9V55OF6n9bZwtEJFLK6gJVdBj8zrQLHj9Lfdn36I7p48lcoG+oo=;5:L/Ie7OjLhreVfvaQi2wnvyVrdUUQj9edwLEfYV3jWmmDHrrWARaUpFT/fKqeFG93Ia4Sj4kzaF0Bi9JqmhNO9CmkwqLSlfV8V7D3VKjYgkF7VVaWAwnW1H9E6/ABCGlIDgdR+qhPnoekdalJZDIgsg==;24:RzK3VbFwRNVvO3lbFQLGTemiVp8xR/Ijx83BbjO5jHIm2QoFmu2Ld2G8XY/4/g0Sss/6aZGa6WyhrjgTfANszxAPMXPIfY1a3g+4BuNtC5U= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics-untrusted: 1;BN3PR03MB1512;7:nEGw23NeXH2AFnY2p3vqCLMXq/Sy4XeS6GSpdxOa49TPCUtBbWcush8gKVz6T9Zjd4JtRegfixQQG2Evof7e23/nmGfGymrZIAAn61OuZ4jDsD9/NQXgPl+c7Ms96vzi68Ipjf7RMmaEnIV9OqMWwJ98TpF0mvTfpinT4Uhw+sDOvMttin7JuZnSqzIKCY2/OPXUsm+iO7nYhn7dQNwLpFAFCkaZgXUR55d3YxgboxJZAJSFnSeS2LnThD3vxagzxmSYi3r6fnmkY5E9cL8W32y3oOehmM+cjACqaYDwXwcJ2TJtmJVL1K5Lr/SE3Ssl+MboihaeRJLda6IRDGYoly5q4eHH1KlnPHC3Du/eUIs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1512 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:66.35.236.236;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(77096005)(1076002)(50466002)(53416004)(189998001)(76176999)(33646002)(50986999)(66066001)(3720700001)(47776003)(2906002)(8676002)(48376002)(15975445007)(2950100002)(6070500001)(97736004)(7520500002)(42882006)(107886002)(15974865002)(6666003)(229853001)(85426001)(6116002)(586003)(105606002)(106466001)(11100500001)(19580395003)(19580405001)(956001)(7416002)(3846002)(92566002)(4326007)(50226002)(4001430100002)(336002)(8936002)(5003940100001)(7736002)(87936001)(86362001)(626004)(7846002)(5660300001)(81166006)(305945005)(68736007)(356003)(81156014)(8666005)(110136003)(7099028)(7059030);DIR:OUT;SFP:1101;SCL:1;SRVR:CY4PR03MB2757;H:sj-itexedge04.altera.priv.altera.com;FPR:;SPF:Fail;PTR:InfoDomainNonexistent;A:0;MX:1;LANG:en; X-Microsoft-Exchange-Diagnostics: 1;BN1AFFO11FD027;1:Xq5DTP1vL9KlqovEhaUHnBqEHuKPKERMmJRBhq3czD5af3c6i5gEK5eNOGybjJezN/kZd5OjjGu9XXc+hxm/qw+xm506slMKOy3QJtnz/UlaNHQnwNkK5ubyXXlur1wLAXnDGK1nKK4vC8YP3SqVvF/2GFWMfJC8tcPUM7WEcK3A9fOLsrl9n1X2EWCmoX7zi8i3mmR5RcVZ81rdq+PBhjZ4Ym1PUcvDooITUw7W1i49KfIwAqxfk5s79MBNsAVlKQf6JsqV4kJRQC2R0gb6mJfkoPIL2JMyO/KY+xhRtFhOqV8/LjJG7iFMGtX4SdRduKjvs4JLJ5zWphAn6B81DTwGAW7lqm7dl6zbqTOVGKMXi7+mKZ8KCZj29rj4onO1fMhzGHMWt+dxFHIy37qCEq+L6Kn2tlrJRGr1uCE7Lgmwiw+nahW4q7H+jiVAE4FMyJx4bhvyE0svcHSBMSjs6cQ8AdJoyv2SoQ101MD7yJxj56T3R/6ThNlnj+noxHg1vKAbaY62NgSiGD+vR4xjM8kR9zJpp0JbcLKSTqFnxE6erKTEJn2KEA+bF0OKqvtgUgNKAWnF+MRWkJE6VlOVbbISf/iKhqb9gTsHm6aKByKEjBD8zQAD6s8VQn/sp4yt X-MS-Exchange-Transport-CrossTenantHeadersStripped: BN1AFFO11FD027.protection.gbl X-Microsoft-Exchange-Diagnostics: 1;CY4PR03MB2757;2:j6AEKIKNa4gjlDbDGGiVT5PzlvdOkqaHg9aE6+lt3Bk81VzwVTMK9oPW1Vrd6ctbyWoKPymIe6sZcuZqshLWiE1ocSNoI1jqWzXvqF00OJHDBw2cn88iIuQCXtRsXYXjY8MLHGAzF3Pmjkw3MHcmpt2qSc8S+FQbRSbNivF9BGmci9ylqJq/ts3KuHwkbIZiomBZY9pbZWcSn3CmHBCAdA==;3:29Ar3tl/Hm9XI7IgzW7YeWde4Imi2fGYvHXOgO4ZUXBbwd+QEjSyAzqmNiFmvG6N5x+0a19aZx4rLBc3CSDFrrNCiAnC7AzzJ/St3wX3TRCBWn5vHlm02qoIQXevIYueCoZEZU0JAFsImHBtyAQPWmLSJKksnHtjysRlD28oZvnFAjjiXDptcZAmWEnSoMUUtRVOUflmRT8EKwBx15Fwj14ga+niX1mpiFakEAFanOd7D88QD3MB04YlNJnWAfDVfMXcIalj1hOqcyuJ3ge6Sg==;25:KaH1uOg+rOmYtVg8G0DKv4ZTCYT8dFa4z6VG8b+Mc6TrRIwPKNYY68SixG07A5qbQJtdJbQRLEYYecdiQkyf0PWex2IMOIMgKn3iRt5eCk7JQrWNjbUgVCRMIf/+6LoY5qNBuYTZDrSfPWrmWrnSGU8f3FBWoSYpvRPMYHx8DBF4FjGO+NaiVDLlOQ8hxwu9kfDo62EmEtz30HgKVoyRFtgtZv1cYl4XACIllFMmNVPkNSJJbprH0ZfNJVmvdobzMAqfAYXpK2XhN4RUSJKXbkGKnUZX8a4g25KaKZsIb0Yx8Lqp53jkomA0yi8PvWPvtST0S4K4xF4ZpxnPmVZ7hiXv5ctyH1wfskD/cv7nFODy9lGRtvzeEd6lH0qofkd9GF2TYkfYIRRJgAtvyxSE/WCCs12QNI6Iy9XJp+NvL8K+joEdLZcoBZiKvxJxrPjhc+f/BIqkEcHUvS8MrKqgXw== X-DkimResult-Test: Passed X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(3001016);SRVR:CY4PR03MB2757; X-Microsoft-Exchange-Diagnostics: 1;CY4PR03MB2757;31:fMjchXchm3UEzqtP+SScV7l8GItcMM3TMgmloOZodU7NFuCad111zzwpCjV+gKqD5LYZ7scYf0Fe9cuLydXGrA7u8Y8jP5QK3/6BWVU0q9ajiUDcet5El0xrcKIsAv4XsU1aB4RUyRQ7c9INRazRfuOa6LPlDgpuJxvn2RZYakoqFs9Lx+lMN7HE1qDQvjsZMBP7RVqcGnGvbaA1e6yDW8nEpIVOA1jJ9kHWXoxt/zNe40mOCoGti0UDakxuUYGPEtTFikJF+gvrTca5hJyiQcbBf8kEaepREIUZwkElW1E=;20:QUhuBRRFoKQ9kX48zGOH26/+ntFtyuhWWxPQZxJAsBUQqMPi9sr7x2LJYP4Piqq1rTUedKJbj77qaMnh3oT78wL0M370unEHy+xgTQCTVy55yy4owWkCaOpM4pUOq9r+VL9MJiKdrJejedvpvtnC44E70QCyITyT5xH3sKyArns= X-Microsoft-Exchange-Diagnostics: 1;CY4PR03MB2757;4:98FnUj0TfwgQyqt8qm2x2pSIqU1iuXWCNZEyTclpdEiMLJ26JzLCcANgX1X7xB+11+UP3lnwvxGcQ6EPOOXDFjhFvQD/T2LZjl1kqqD6m3sRc/skLWFNDWtPy8Xi+O1ZizeGTZ2O04BiqomHv8wiP7c4fnmM2bqG6pJBsnSsa5NdGpBGvwfEeeMN+JKR0jdqkrviCxGvoTJgnhoo1+6j4YRNppf59vFQ7YvMOH6qptlNbQcNJNnlVUOdOY+n+7NKPJDjsmtRj26v6czt4EGLG9D+aCV0cd24nYUgMZgAfnBUuzeMdIHCwy8Sf93KtGWQeU/hipj1BsWike5TKfzVPnHFKm2Rb7A3BFdhQp1hPcVCUERMHs+mDfrmvVqdfikWQ20TJkveHw8j/Kl6Hp+l7n6YrUS219A5ZFvMDGeTQH3O99ccCKRx/W3Qv0EZrFRZzsAoJmrDazdTMAZMzl+qAA0tYeCnEQ7JB9Pp2RL9qvD+1iBSWgIM6KFamF5eJGur+KYMRtdkXk5EYbVTiBNXy20im2r6aMaLtjcK2DdCs0q7rimCrZ9RJMqi/C1IAWENaA6RkDQmTtdtwyzTtsMEPhuy1hBa7L94j/X1j+gMpJVhqII3PwM7Cw+4Pg/urLzBF7txwFA5iOZFObWfN39Fc7P7GmHs7fWe4PrilmVNW5HJaV4BUJJ3Y5+CK3+Zn8ngYVYNFstd28dQXVgI6NgmZ4PAOUYf26lsFbf90BGwzhgZSiLV+TWZhajTpg+qLRvy X-Forefront-PRVS: 0098BA6C6C X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;CY4PR03MB2757;23:oNBpDXbIsVhcShSPxDXdxpko8DKEr871SNn1puGvI?= =?us-ascii?Q?1AkpMtmdokno/oKQXUxR3080K9nlPpMJ4jFePCNIAWoZfj/s2RVF8oK3JKtt?= =?us-ascii?Q?1d8hWsHrXqKMJUFiCZFhSpzSXCwGvWnLa7n24+1Wv/4p+7+QOoFfUTaVchMt?= =?us-ascii?Q?/idZ4NDZOF7HePh4sawsoKidqtXbqRL6F2gOXJjF0iZfVDPLhYfyNhpj5i0w?= =?us-ascii?Q?yvuBD4kdDEer0tBIFC79ztsc7x/M/p95LcjUGx9yddkkmq/ymkV1GZ63zJGX?= =?us-ascii?Q?P3aRA4rRkLdCf/3jY+BHdKJ/e8xL6UzQxUadqTA9cwPvqVXi7wit2Qm8YJBw?= =?us-ascii?Q?UluwII8Yv/5OsHhZKsqtv7z54D18rAy0QkneSlHC5oWG/vOhUtovcsSIoSB/?= =?us-ascii?Q?unkAUoPwPWgX0eupfa2sx8Ssw4NIENCTlpzca9RLQ7csTdZ27J+/NUuPTvzm?= =?us-ascii?Q?XsyiNmnLK1owxt3Iz6I2J+fsMNz8bLR141NyM4uKWrGzrWFnkEBdb11OnXLx?= =?us-ascii?Q?dhBjHLHi6b9yCMxx3YHbs5rJjrt8MHpntEzibrk2r//M30fFqNuSaS6rhHAv?= =?us-ascii?Q?0iCEElVP9jHSjeXhOA/9nSMEN9VIXWz1JRQuqQA5gPgnqwqQIDuWeHeFDkf5?= =?us-ascii?Q?XptPspNcqG23b1fvWRFBECNnB3P/Y1Zm4KRuNUXbn5JWG3HeGU4we3SHgQED?= =?us-ascii?Q?JOKZmR7fBlciGjpRmIJQeavQwuxZ6G2wqMUpjcZnkR8jee9WOxAOZuRdu3tc?= =?us-ascii?Q?1onEbUvcRWExrahzl6rnL6D4G6Q9Hrw8doudwrRTOoOU4RkajRtNShOGI/Mk?= =?us-ascii?Q?RDvNIu8dA7s0zg/ap+1uLCnhP+p5Ur9sr37vX3L0Np7tP7AoP5/pF2ePibTV?= =?us-ascii?Q?S483W4Yv1+wHM1U0uGHrUIQCw2Rh+OSYkInr+Sq1hE/mXCLwlwng+sNV+S7h?= =?us-ascii?Q?GgoQ7fsPrMdhz39Pd7JmvBWQUYXo+jHL0Fa4C5iYiVzwVyCV+EqCD+6Tl5B8?= =?us-ascii?Q?vfm1WUrWP7FrMBJasHbKgHDZJqWdk3x1VJjAmKWRBrsf9BFlVYkBSQa+lOCo?= =?us-ascii?Q?LzkqatEn5fVVanSsER6SHTKhqI5rWyhNVNX0365cDoDfgw7SQkhDPIUraJ10?= =?us-ascii?Q?RPAfXpV2Fvt0lBecI/iKnK8TKBOMl4+cHsg6fJ32P6W7xj9ghSXttcX8IV5/?= =?us-ascii?Q?TkpFONpdRxpzmfQsBaEEIbp2yGDbMT9Gb3vhmmp7BeRSAYFt1c3MT+BlOyhp?= =?us-ascii?Q?94WX9BGZA7IV3kpcmk0hKoSu+FpnUbNF1zPyw7hxtUBpji/v1p0heBI3PkLT?= =?us-ascii?Q?O+QVqntBF+WUCikKXTooZ2r6JPlZrL3wodneAxRWamfirVw67pcjVih+HF8g?= =?us-ascii?Q?jZNjcAuV8NC65bk44E+Paa0maJwqiobsUJYU/UHyL0Mk1WXkYbQ8DTVCDN2N?= =?us-ascii?Q?iMGq2zI1gfbAMcAZlET+jkXJPaJ67FrKUqDupKCh+mMc4QXXQDzumT6YO0q5?= =?us-ascii?Q?aYFSDsD9da0YtDJzkUjCTpPX6mVxxpEdLBq/8nFX9PpMoLMFKihHAyx?= X-Microsoft-Exchange-Diagnostics: 1;CY4PR03MB2757;6:uJ1Z/hQld8E03j/3VUGp7BMgzOMaaiywHEytqyAXVFPdWUd/ZCQXyOp/mKLQOUSl7Nb1+wWmLNEzZT0ehOy3OeoDLsgrNUdE0NISxDQi8z+D8rd97UYjSaHEgeQodV5UVaLJnjBI//XIVXYTXhwVoL4c9YwYUepB+2IdTX8gC7T2B3a0/SlDShnq6Z6NDtp9W/p9l7K0NcP0dyzReEgfCqStYF+WzXbiuAqKb2HRzJEjrr1e/5qrGr4z2ZD1tth/z3ylMOxEGxRvtTA/yAnHEuH8Z876Z35B45SrWrF1swqs5ayqNgi2lrl/GpLd6zaYz5K9XO80YmUtEkVdHXeWa7Zd1E//D3rX0ebGkFIr+5E=;5:uVpGo/MhJK1B9ypLl20npP/l+DMzTnDI55RzgLPG9KgYzcSTZF0JQUGcGdwZoe7Ule6L8AtKXFhMo4aGPr5beQZUr5voTQCB8KzwkHCaGL9tfDBEjza02UI6/wrQuNg669tclfmmayw/UGrvzaMDew==;24:UkZrSR71UE969g4xALiN/08aXoQYbozkKsN9uTYqhNIaotZ8x4Gk9pg8yw3mL1xIAjrDr1qGzXGYgEqL2m6o5JnADUDFb1lFLpo/K/jIhn8= X-Microsoft-Exchange-Diagnostics: 1;CY4PR03MB2757;7:sl+GG6e4T6bNXF9Ef6HGCS9IZWMLX1o+A6DlIgbQmUdg97bykL00MMwfhGRUn07rmuzSR5ydtxvkxNNadglwJ7NnoidmSAQ71abD1il9V46fqUdzFiGLs7oXy3JScg4TuKgF9qUIlmEZAsb10JS1HdH7OsfW4runIMdkbK4qy7KeHSeQeoXuo6dgM+WlpFtbUT41SDTElZnyG5euGU7cSve7dvcG0zWu2kdl9eeiBATiCJcUSibmiJkwsLkXYCB+qPrKKEPOX7TlMrVpZc9TnLy/L2FTjk7ex0kP2PQ+/SBo1+TAPYHjWm99oq53FrCcVD0/i2PGdTYi/bnDjOI++Q== X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2016 16:09:50.3600 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a;Ip=[66.35.236.236];Helo=[sj-itexedge04.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2757 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 20437 Lines: 551 New bindings document for FPGA Region to support programming FPGA's under Device Tree control Signed-off-by: Alan Tull Signed-off-by: Moritz Fischer Reviewed-by: Rob Herring --- v9: initial version added to this patchset v10: s/fpga/FPGA/g replace DT overlay example with slightly more complicated example move to staging/simple-fpga-bus v11: No change in this patch for v11 of the patch set v12: Moved out of staging. Changed to use FPGA bridges framework instead of resets for bridges. v13: bridge@0xff20000 -> bridge@ff200000, etc Leave out directly talking about overlays Remove regs and clocks directly under simple-fpga-bus in example Use common "firmware-name" binding instead of "fpga-firmware" v14: Use firmware-name in bindings description Call it FPGA Area Remove bindings that specify FPGA Manager and FPGA Bridges v15: Cleanup as per Rob's comments Combine usage doc with bindings document Document as being Altera specific Additions and changes to add FPGA Bus v16: Reworked to document FPGA Regions rename altera-fpga-bus-fpga-area.txt -> fpga-region.txt Remove references that made it sound exclusive to Altera Remove altr, prefix from fpga-bus and fpga-area compatible strings Added Moritz' usage example with Xilinx Cleaned up unit addresses v17: Lots of rewrites to try to make things clearer Clarify that overlay can be rejected if FPGA isn't programmed Add external-fpga-config binding already used in u-boot Change partial-reconfig binding to partial-fpga-config to align with existing u-boot binding format *-fpga-config Add a document from Xilinx' website v18: Fix node names underscores to be hyphens Fix copy/pasted duplicate nodes in diagram v19: Fix more underscores Make FPGA regions to be children of bridges General cleanup and clarification v20: Add Rob's reviewed-by --- .../devicetree/bindings/fpga/fpga-region.txt | 494 +++++++++++++++++++++ 1 file changed, 494 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/fpga-region.txt diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt new file mode 100644 index 0000000..3b32ba1 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -0,0 +1,494 @@ +FPGA Region Device Tree Binding + +Alan Tull 2016 + + CONTENTS + - Introduction + - Terminology + - Sequence + - FPGA Region + - Supported Use Models + - Device Tree Examples + - Constraints + + +Introduction +============ + +FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in +the Device Tree. FPGA Regions provide a way to program FPGAs under device tree +control. + +This device tree binding document hits some of the high points of FPGA usage and +attempts to include terminology used by both major FPGA manufacturers. This +document isn't a replacement for any manufacturers specifications for FPGA +usage. + + +Terminology +=========== + +Full Reconfiguration + * The entire FPGA is programmed. + +Partial Reconfiguration (PR) + * A section of an FPGA is reprogrammed while the rest of the FPGA is not + affected. + * Not all FPGA's support PR. + +Partial Reconfiguration Region (PRR) + * Also called a "reconfigurable partition" + * A PRR is a specific section of a FPGA reserved for reconfiguration. + * A base (or static) FPGA image may create a set of PRR's that later may + be independently reprogrammed many times. + * The size and specific location of each PRR is fixed. + * The connections at the edge of each PRR are fixed. The image that is loaded + into a PRR must fit and must use a subset of the region's connections. + * The busses within the FPGA are split such that each region gets its own + branch that may be gated independently. + +Persona + * Also called a "partial bit stream" + * An FPGA image that is designed to be loaded into a PRR. There may be + any number of personas designed to fit into a PRR, but only one at at time + may be loaded. + * A persona may create more regions. + +FPGA Bridge + * FPGA Bridges gate bus signals between a host and FPGA. + * FPGA Bridges should be disabled while the FPGA is being programmed to + prevent spurious signals on the cpu bus and to the soft logic. + * FPGA bridges may be actual hardware or soft logic on an FPGA. + * During Full Reconfiguration, hardware bridges between the host and FPGA + will be disabled. + * During Partial Reconfiguration of a specific region, that region's bridge + will be used to gate the busses. Traffic to other regions is not affected. + * In some implementations, the FPGA Manager transparantly handles gating the + buses, eliminating the need to show the hardware FPGA bridges in the + device tree. + * An FPGA image may create a set of reprogrammable regions, each having its + own bridge and its own split of the busses in the FPGA. + +FPGA Manager + * An FPGA Manager is a hardware block that programs an FPGA under the control + of a host processor. + +Base Image + * Also called the "static image" + * An FPGA image that is designed to do full reconfiguration of the FPGA. + * A base image may set up a set of partial reconfiguration regions that may + later be reprogrammed. + + ---------------- ---------------------------------- + | Host CPU | | FPGA | + | | | | + | ----| | ----------- -------- | + | | H | | |==>| Bridge0 |<==>| PRR0 | | + | | W | | | ----------- -------- | + | | | | | | + | | B |<=====>|<==| ----------- -------- | + | | R | | |==>| Bridge1 |<==>| PRR1 | | + | | I | | | ----------- -------- | + | | D | | | | + | | G | | | ----------- -------- | + | | E | | |==>| Bridge2 |<==>| PRR2 | | + | ----| | ----------- -------- | + | | | | + ---------------- ---------------------------------- + +Figure 1: An FPGA set up with a base image that created three regions. Each +region (PRR0-2) gets its own split of the busses that is independently gated by +a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be +reprogrammed independently while the rest of the system continues to function. + + +Sequence +======== + +When a DT overlay that targets a FPGA Region is applied, the FPGA Region will +do the following: + + 1. Disable appropriate FPGA bridges. + 2. Program the FPGA using the FPGA manager. + 3. Enable the FPGA bridges. + 4. The Device Tree overlay is accepted into the live tree. + 5. Child devices are populated. + +When the overlay is removed, the child nodes will be removed and the FPGA Region +will disable the bridges. + + +FPGA Region +=========== + +FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA +Region brings together the elements needed to program on a running system and +add the child devices: + + * FPGA Manager + * FPGA Bridges + * image-specific information needed to to the programming. + * child nodes + +The intended use is that a Device Tree overlay (DTO) can be used to reprogram an +FPGA while an operating system is running. + +An FPGA Region that exists in the live Device Tree reflects the current state. +If the live tree shows a "firmware-name" property or child nodes under a FPGA +Region, the FPGA already has been programmed. A DTO that targets a FPGA Region +and adds the "firmware-name" property is taken as a request to reprogram the +FPGA. After reprogramming is successful, the overlay is accepted into the live +tree. + +The base FPGA Region in the device tree represents the FPGA and supports full +reconfiguration. It must include a phandle to an FPGA Manager. The base +FPGA region will be the child of one of the hardware bridges (the bridge that +allows register access) between the cpu and the FPGA. If there are more than +one bridge to control during FPGA programming, the region will also contain a +list of phandles to the additional hardware FPGA Bridges. + +For partial reconfiguration (PR), each PR region will have an FPGA Region. +These FPGA regions are children of FPGA bridges which are then children of the +base FPGA region. The "Full Reconfiguration to add PRR's" example below shows +this. + +If an FPGA Region does not specify a FPGA Manager, it will inherit the FPGA +Manager specified by its ancestor FPGA Region. This supports both the case +where the same FPGA Manager is used for all of a FPGA as well the case where +a different FPGA Manager is used for each region. + +FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents +shutting down bridges that are upstream from the other active regions while one +region is getting reconfigured (see Figure 1 above). During PR, the FPGA's +hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges +within the static image of the FPGA. + +Required properties: +- compatible : should contain "fpga-region" +- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions + inherit this property from their ancestor regions. A fpga-mgr property + in a region will override any inherited FPGA manager. +- #address-cells, #size-cells, ranges : must be present to handle address space + mapping for child nodes. + +Optional properties: +- firmware-name : should contain the name of an FPGA image file located on the + firmware search path. If this property shows up in a live device tree + it indicates that the FPGA has already been programmed with this image. + If this property is in an overlay targeting a FPGA region, it is a + request to program the FPGA with that image. +- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be + controlled during FPGA programming along with the parent FPGA bridge. + This property is optional if the FPGA Manager handles the bridges. + If the fpga-region is the child of a fpga-bridge, the list should not + contain the parent bridge. +- partial-fpga-config : boolean, set if partial reconfiguration is to be done, + otherwise full reconfiguration is done. +- external-fpga-config : boolean, set if the FPGA has already been configured + prior to OS boot up. +- region-unfreeze-timeout-us : The maximum time in microseconds to wait for + bridges to successfully become enabled after the region has been + programmed. +- region-freeze-timeout-us : The maximum time in microseconds to wait for + bridges to successfully become disabled before the region has been + programmed. +- child nodes : devices in the FPGA after programming. + +In the example below, when an overlay is applied targeting fpga-region0, +fpga_mgr is used to program the FPGA. Two bridges are controlled during +programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is +the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the +fpga-bridges property. During programming, these bridges are disabled, the +firmware specified in the overlay is loaded to the FPGA using the FPGA manager +specified in the region. If FPGA programming succeeds, the bridges are +reenabled and the overlay makes it into the live device tree. The child devices +are then populated. If FPGA programming fails, the bridges are left disabled +and the overlay is rejected. The overlay's ranges property maps the lwhps +bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by +the two child devices. + +Example: +Base tree contains: + + fpga_mgr: fpga-mgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x20>; + interrupts = <0 175 4>; + }; + + fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fpga_region0: fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + }; + + fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; + clocks = <&l4_main_clk>; + }; + +Overlay contains: + +/dts-v1/ /plugin/; +/ { + fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "soc_system.rbf"; + fpga-bridges = <&fpga_bridge1>; + ranges = <0x20000 0xff200000 0x100000>, + <0x0 0xc0000000 0x20000000>; + + gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + altr,gpio-bank-width = <4>; + #gpio-cells = <2>; + clocks = <2>; + gpio-controller; + }; + + onchip-memory { + device_type = "memory"; + compatible = "altr,onchipmem-15.1"; + reg = <0x0 0x10000>; + }; + }; + }; +}; + + +Supported Use Models +==================== + +In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and +a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some +uses are specific to a FPGA device. + + * No FPGA Bridges + In this case, the FPGA Manager which programs the FPGA also handles the + bridges behind the scenes. No FPGA Bridge devices are needed for full + reconfiguration. + + * Full reconfiguration with hardware bridges + In this case, there are hardware bridges between the processor and FPGA that + need to be controlled during full reconfiguration. Before the overlay is + applied, the live DT must include the FPGA Manager, FPGA Bridges, and a + FPGA Region. The FPGA Region is the child of the bridge that allows + register access to the FPGA. Additional bridges may be listed in a + fpga-bridges property in the FPGA region or in the device tree overlay. + + * Partial reconfiguration with bridges in the FPGA + In this case, the FPGA will have one or more PRR's that may be programmed + separately while the rest of the FPGA can remain active. To manage this, + bridges need to exist in the FPGA that can gate the buses going to each FPGA + region while the buses are enabled for other sections. Before any partial + reconfiguration can be done, a base FPGA image must be loaded which includes + PRR's with FPGA bridges. The device tree should have a FPGA region for each + PRR. + +Device Tree Examples +==================== + +The intention of this section is to give some simple examples, focusing on +the placement of the elements detailed above, especially: + * FPGA Manager + * FPGA Bridges + * FPGA Region + * ranges + * target-path or target + +For the purposes of this section, I'm dividing the Device Tree into two parts, +each with its own requirements. The two parts are: + * The live DT prior to the overlay being added + * The DT overlay + +The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA +Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle +to handle programming the FPGA. If the FPGA Region is the child of another FPGA +Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved, +they are specified in the FPGA Region by the "fpga-bridges" property. During +FPGA programming, the FPGA Region will disable the bridges that are in its +"fpga-bridges" list and will re-enable them after FPGA programming has +succeeded. + +The Device Tree Overlay will contain: + * "target-path" or "target" + The insertion point where the the contents of the overlay will go into the + live tree. target-path is a full path, while target is a phandle. + * "ranges" + The address space mapping from processor to FPGA bus(ses). + * "firmware-name" + Specifies the name of the FPGA image file on the firmware search + path. The search path is described in the firmware class documentation. + * "partial-fpga-config" + This binding is a boolean and should be present if partial reconfiguration + is to be done. + * child nodes corresponding to hardware that will be loaded in this region of + the FPGA. + +Device Tree Example: Full Reconfiguration without Bridges +========================================================= + +Live Device Tree contains: + fpga_mgr0: fpga-mgr@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; + clocks = <&clkc 12>; + clock-names = "ref_clk"; + syscon = <&slcr>; + }; + + fpga_region0: fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + +DT Overlay contains: +/dts-v1/ /plugin/; +/ { +fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "zynq-gpio.bin"; + + gpio1: gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + gpio-controller; + #gpio-cells = <0x2>; + xlnx,gpio-width= <0x6>; + }; + }; +}; + +Device Tree Example: Full Reconfiguration to add PRR's +====================================================== + +The base FPGA Region is specified similar to the first example above. + +This example programs the FPGA to have two regions that can later be partially +configured. Each region has its own bridge in the FPGA fabric. + +DT Overlay contains: +/dts-v1/ /plugin/; +/ { + fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "base.rbf"; + + fpga-bridge@4400 { + compatible = "altr,freeze-bridge"; + reg = <0x4400 0x10>; + + fpga_region1: fpga-region1 { + compatible = "fpga-region"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + }; + + fpga-bridge@4420 { + compatible = "altr,freeze-bridge"; + reg = <0x4420 0x10>; + + fpga_region2: fpga-region2 { + compatible = "fpga-region"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + }; + }; + }; + }; +}; + +Device Tree Example: Partial Reconfiguration +============================================ + +This example reprograms one of the PRR's set up in the previous example. + +The sequence that occurs when this overlay is similar to the above, the only +differences are that the FPGA is partially reconfigured due to the +"partial-fpga-config" boolean and the only bridge that is controlled during +programming is the FPGA based bridge of fpga_region1. + +/dts-v1/ /plugin/; +/ { + fragment@0 { + target = <&fpga_region1>; + #address-cells = <1>; + #size-cells = <1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + firmware-name = "soc_image2.rbf"; + partial-fpga-config; + + gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + clocks = <0x2>; + altr,gpio-bank-width = <0x4>; + resetvalue = <0x0>; + #gpio-cells = <0x2>; + gpio-controller; + }; + }; + }; +}; + +Constraints +=========== + +It is beyond the scope of this document to fully describe all the FPGA design +constraints required to make partial reconfiguration work[1] [2] [3], but a few +deserve quick mention. + +A persona must have boundary connections that line up with those of the partion +or region it is designed to go into. + +During programming, transactions through those connections must be stopped and +the connections must be held at a fixed logic level. This can be achieved by +FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. + +-- +[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf +[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf +[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf -- 2.10.1