Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758387AbcJQRFN (ORCPT ); Mon, 17 Oct 2016 13:05:13 -0400 Received: from bgl-iport-2.cisco.com ([72.163.197.26]:24814 "EHLO bgl-iport-2.cisco.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936303AbcJQRBN (ORCPT ); Mon, 17 Oct 2016 13:01:13 -0400 X-Greylist: delayed 597 seconds by postgrey-1.27 at vger.kernel.org; Mon, 17 Oct 2016 13:01:12 EDT X-IronPort-AV: E=Sophos;i="5.31,357,1473120000"; d="scan'208";a="64144167" From: David Singleton To: Andrew Morton Cc: Steve Shih , xe-kernel@external.cisco.com, Greg Kroah-Hartman , Jiri Slaby , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] tty: serial: 8250: 8250_core: NXP SC16C2552 workaround Date: Mon, 17 Oct 2016 09:51:05 -0700 Message-Id: <20161017165108.29718-2-davsingl@cisco.com> X-Mailer: git-send-email 2.9.3 X-Auto-Response-Suppress: DR, OOF, AutoReply Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 945 Lines: 28 From: Steve Shih NXP SC16C2552 requires that we always write a reset to the RX FIFO and TX FIFO whenever we enable the FIFOs Cc: xe-kernel@external.cisco.com Signed-off-by: Steve Shih Signed-off-by: David Singleton --- drivers/tty/serial/8250/8250_port.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 1bfb6fd..1731b98 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -83,7 +83,8 @@ static const struct serial8250_config uart_config[] = { .name = "16550A", .fifo_size = 16, .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, .rxtrig_bytes = {1, 4, 8, 14}, .flags = UART_CAP_FIFO, }, -- 2.9.3