Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965350AbcJQVeV (ORCPT ); Mon, 17 Oct 2016 17:34:21 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:48400 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965083AbcJQVds (ORCPT ); Mon, 17 Oct 2016 17:33:48 -0400 From: Stefan Agner To: meng.yi@nxp.com, dri-devel@lists.freedesktop.org Cc: alison.wang@freescale.com, jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH v3 3/5] drm/fsl-dcu: do not transfer registers in mode_set_nofb Date: Mon, 17 Oct 2016 14:33:19 -0700 Message-Id: <20161017213321.8074-4-stefan@agner.ch> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20161017213321.8074-1-stefan@agner.ch> References: <20161017213321.8074-1-stefan@agner.ch> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 834 Lines: 23 Do not schedule a transfer of mode settings early. Modes should get applied on on CRTC enable where we also enable the pixel clock. Signed-off-by: Stefan Agner --- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index 3371635..5ad1d68 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); - regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, - DCU_UPDATE_MODE_READREG); return; } -- 2.10.0