Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759656AbcJRKDJ (ORCPT ); Tue, 18 Oct 2016 06:03:09 -0400 Received: from mga04.intel.com ([192.55.52.120]:61634 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753410AbcJRKDB (ORCPT ); Tue, 18 Oct 2016 06:03:01 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,361,1473145200"; d="scan'208";a="20739161" From: Grzegorz Andrejczuk To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org Cc: bp@suse.de, dave.hansen@linux.intel.com, linux-kernel@vger.kernel.org, lukasz.daniluk@intel.com, james.h.cownie@intel.com, jacob.jun.pan@intel.com, Grzegorz Andrejczuk Subject: [PATCH v4 1/4] x86/phi: Add R3MWAIT register and bit to msr-info.h Date: Tue, 18 Oct 2016 12:02:48 +0200 Message-Id: <1476784971-23872-2-git-send-email-grzegorz.andrejczuk@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1476784971-23872-1-git-send-email-grzegorz.andrejczuk@intel.com> References: <1476784971-23872-1-git-send-email-grzegorz.andrejczuk@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1602 Lines: 41 Intel Xeon Phi x200 (codenamed Knights Landing) has MSR MISC_THD_FEATURE_ENABLE 0x140. Setting 2nd bit of this register makes MONITOR and MWAIT instructions do not cause invalid-opcode exception when called from ring different than 0. Hex Dec Name Scope 140H 320 MISC_THD_FEATURE_ENABLE Thread 0 Reserved 1 if set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1. 63:2 Reserved Signed-off-by: Grzegorz Andrejczuk --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 56f4c66..df9d8d3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -540,6 +540,11 @@ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ +#define MSR_PHI_MISC_THD_FEATURE 0x00000140 +#define MSR_PHI_MISC_THD_FEATURE_R3MWAIT_BIT 1 +#define MSR_PHI_MISC_THD_FEATURE_R3MWAIT (1ULL << MSR_PHI_MISC_THD_FEATURE_R3MWAIT_BIT) + #define MSR_IA32_TSC_DEADLINE 0x000006E0 /* P4/Xeon+ specific */ -- 2.5.1